16 SPI
16-6
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Control Register Details
16.7
7.1 List of SPI Registers
Table 16.
Address
Register name
Function
0x4320
SPI_ST0
SPI Ch.0 Status Register
Indicates transfer and buffer statuses.
0x4322
SPI_TXD0
SPI Ch.0 Transmit Data Register
Transmit data
0x4324
SPI_RXD0
SPI Ch.0 Receive Data Register
Receive data
0x4326
SPI_CTL0
SPI Ch.0 Control Register
Sets the SPI mode and enables data transfer.
0x4380
SPI_ST1
SPI Ch.1 Status Register
Indicates transfer and buffer statuses.
0x4382
SPI_TXD1
SPI Ch.1 Transmit Data Register
Transmit data
0x4384
SPI_RXD1
SPI Ch.1 Receive Data Register
Receive data
0x4386
SPI_CTL1
SPI Ch.1 Control Register
Sets the SPI mode and enables data transfer.
0x43a0
SPI_ST2
SPI Ch.2 Status Register
Indicates transfer and buffer statuses.
0x43a2
SPI_TXD2
SPI Ch.2 Transmit Data Register
Transmit data
0x43a4
SPI_RXD2
SPI Ch.2 Receive Data Register
Receive data
0x43a6
SPI_CTL2
SPI Ch.2 Control Register
Sets the SPI mode and enables data transfer.
The SPI registers are described in detail below. These are 16-bit registers.
Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
SPI Ch.x Status Registers (SPI_STx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
SPI Ch.x Status
Register
(SPI_STx)
0x4320
0x4380
0x43a0
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2
SPBSY
Transfer busy flag (master)
1 Busy
0 Idle
0
R
ss signal low flag (slave)
1 ss = L
0 ss = H
D1
SPRBF
Receive data buffer full flag
1 Full
0 Not full
0
R
D0
SPTBE
Transmit data buffer empty flag
1 Empty
0 Not empty
1
R
D[15:3]
Reserved
D2
SPBSY: Transfer Busy Flag Bit (Master Mode)/ss Signal Low Flag Bit (Slave Mode)
Master mode
Indicates the SPI transfer status.
1 (R):
Operating
0 (R):
Standby (default)
SPBSY is set to 1 when the SPI starts data transfer in master mode and is maintained at 1 while transfer
is underway. It is cleared to 0 once the transfer is complete.
Slave mode
Indicates the slave selection (#SPISSx) signal status.
1 (R):
Low level (this SPI is selected)
0 (R):
High level (this SPI is not selected) (default)
SPBSY is set to 1 when the master device asserts the #SPISSx signal to select this SPI module (slave
device). It is returned to 0 when the master device clears the SPI module selection by negating the
#SPISSx signal.
D1
SPRBF: Receive Data Buffer Full Flag Bit
Indicates the receive data buffer status.
1 (R):
Data full
0 (R):
No data (default)
SPRBF is set to 1 when data received in the shift register is sent to the receive data buffer (when receiv-
ing is completed), indicating that the data can be read. It reverts to 0 once the buffer data is read from
the SPI_RXDx register.