19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
19-18
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
US_SCKx pin (input)
US_SCKx pin (output)
US_SDIx pin (input)
US_SDIx pin (output)
ISTGMOD[2:0]
ISTG (write)
ISBSY
ISSTA[2:0]
RD[7:0]
ISIF
Interrupt
A6
0x0
0x3
0x4
0x3
A5
A4
A3
A2
A1
A0
R/W = 0
ACK
Start
condition
Slave address reception
Data reception
Start condition
detected
ACK
sent
Receive
buffer full
* Reset by writing 1
*
0x0
D7
D6
(1) Start condition
→ Data reception
0x3
0x5
0x4
0x5
0x3
Received data (n - 1)
0x3
0x5
0x3
0x4
0x1
Received data n
Receive
buffer full
ACK
sent
Stop condition
detected
Receive
buffer full
NAK
sent
*
* Reset by writing 1
US_SCKx pin (input)
US_SCKx pin (output)
US_SDIx pin (input)
US_SDIx pin (output)
ISTGMOD[2:0]
ISTG (write)
ISBSY
ISSTA[2:0]
RD[7:0]
ISIF
Interrupt
Data reception
Stop
condition
D5
D4
D3
D2
D1
D0
D7
D6
D0
ACK
(2) Data reception
→ Stop condition
5.3.14 I
Figure 19.
2C Slave Data Receiving Timing Chart
Note: The timing chart above shows a basic transfer operation that does not include an actual I2C trans-
fer procedure. See “Receiving control byte in I2C slave mode” in “19.9 Precautions.”
(1) Waiting for start condition
The procedure is the same as that of data transmission in I2C slave mode.
(2) Receiving slave address and transfer direction data bit
The procedure is the same as that of data transmission in I2C slave mode.
(3) Data reception
When the transfer direction bit received with the slave address in Step (2) is 0, start data reception by set-
ting ISTGMOD[2:0] to 0x3 and writing 1 to ISTG.
When clocks are input, the I2C controller loads the US_SDOx pin status to the shift register in sync with
each clock. The received data is loaded to the receive data buffer (RD[7:0]/USI_RDx register) once the 8-bit
data has been received in the shift register.
Writing 1 to ISTG sets ISBSY to 1. When the received data is loaded to the receive data buffer, ISBSY
reverts to 0 and ISSTA[2:0] is set to 0x3 (receive data buffer full). An interrupt request can be generated at
this point. Read the received data from the receive data buffer using this interrupt.
It is necessary to send back an ACK or NAK to the master device after an 8-bit data has been received.
To send back an ACK, set ISTGMOD[2:0] to 0x4 and write 1 to ISTG. To send back a NAK, set
ISTGMOD[2:0] to 0x5 and write 1 to ISTG.
ISBSY is set to 1 while an ACK/NAK is being sent and it reverts to 0 when the transmission has completed.
An interrupt request can be generated at this point. When an ACK or NAK has been sent, ISSTA[2:0] is set
to 0x4.
Repeat an 8-bit data reception and ACK (NAK) transmission for the required number of times.