22 ON-CHIP DEBUGGER (DBG)
22-2
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Additional Debugging Function
22.3
The S1C17554/564 expands the following on-chip debugging functions of the S1C17 Core.
Branching destination in debug mode
When a debug interrupt is generated, the S1C17 Core enters debug mode and branches to the debug processing
routine. In this process, the S1C17 Core is designed to branch to address 0xfffc00. In addition to this branching
destination, the S1C17554/564 also allows designation of address 0x0 (beginning address of the internal RAM)
as the branching destination when debug mode is activated. The branching destination address is selected using
DBADR/MISC_IRAMSZ register. When the DBADR is set to 0 (default), the branching destination is set to
0xfffc00. When it is set to 1, the branching destination is set to 0x0.
Adding instruction breaks
The S1C17 Core supports two instruction breaks (hardware PC breaks). The S1C17554/564 increased this
number to five, adding the control bits and registers given below.
IBE2/DCR register:
Enables instruction breaks #2.
IBE3/DCR register:
Enables instruction breaks #3.
IBE4/DCR register:
Enables instruction breaks #4.
IBAR2[23:0]/IBAR2 register: Set instruction break address #2.
IBAR3[23:0]/IBAR3 register: Set instruction break address #3.
IBAR4[23:0]/IBAR4 register: Set instruction break address #4.
Note that the debugger included in the S5U1C17001C (Ver. 1.2.1) or later is required to use five hardware PC
breaks.
Control Register Details
22.4
4.1 List of Debug Registers
Table 22.
Address
Register name
Function
0x4020
MISC_DMODE1 Debug Mode Control Register 1
Enables peripheral operations in debug mode (PCLK).
0x5322
MISC_DMODE2 Debug Mode Control Register 2
Enables peripheral operations in debug mode (except PCLK).
0x5326
MISC_IRAMSZ IRAM Size Select Register
Selects the IRAM size.
0xffff90
DBRAM
Debug RAM Base Register
Indicates the debug RAM base address.
0xffffa0
DCR
Debug Control Register
Controls debugging.
0xffffb8
IBAR2
Instruction Break Address Register 2
Sets Instruction break address #2.
0xffffbc
IBAR3
Instruction Break Address Register 3
Sets Instruction break address #3.
0xffffd0
IBAR4
Instruction Break Address Register 4
Sets Instruction break address #4.
The debug registers are described in detail below.
Notes: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
For debug registers not described here, refer to the S1C17 Core Manual.
Debug Mode Control Register 1 (MISC_DMODE1)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Debug Mode
Control
Register 1
(MISC_DMODE1)
0x4020
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1
DBRUN1
Run/stop select in debug mode
1 Run
0 Stop
0
R/W
D0
–
reserved
–
0 when being read.
D[7:2]
Reserved
D1
DBRUN1: Run/Stop Select Bit in Debug Mode
Selects the operating status of the peripheral circuits that operate with PCLK in debug mode.
1 (R/W): Run
0 (R/W): Stop (default)