11 16-BIT PWM TIMERS (T16A)
11-14
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
D1
MULTIMD: Multi-Comparator/Capture Mode Select Bit (T16A_CLK0 register)
Sets the T16A module to multi-comparator/capture mode.
1 (R/W): Multi-comparator/capture mode
0 (R/W): Normal channel mode (default)
In multi-comparator/capture mode, the clock for Ch.0 configured in the T16A_CLK0 register is sup-
plied to all timer channels. In normal channel mode, different clock configured for each channel indi-
vidually is supplied to the respective counter.
D1
Reserved (T16A_CLK1–3 registers)
D0
CLKEN: Count Clock Enable Bit
Enables or disables the count clock supply to the counter.
1 (R/W): Enabled (on)
0 (R/W): Disabled (off) (default)
The CLKEN default setting is 0, which disables the clock supply. Setting CLKEN to 1 sends the clock
selected as above to the counter. If timer operation is not required, disable the clock supply to reduce
current consumption.
T16A Counter Ch.x Control Registers (T16A_CTLx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16A Counter
Ch.x Control
Register
(T16A_CTLx)
0x5400
0x5420
0x5440
0x5460
(16 bits)
D15–6 –
reserved
–
0 when being read.
D5–4 CCABCNT
[1:0]
Counter select
CCABCNT[1:0] Counter Ch.
0x0 R/W
0x3
0x2
0x1
0x0
Ch.3
Ch.2
Ch.1
Ch.0
D3
CBUFEN
Compare buffer enable
1 Enable
0 Disable
0
R/W
D2
TRMD
Count mode select
1 One-shot
0 Repeat
0
R/W
D1
PRESET
Counter reset
1 Reset
0 Ignored
0
W 0 when being read.
D0
PRUN
Counter run/stop control
1 Run
0 Stop
0
R/W
D[15:6]
Reserved
D[5:4]
CCABCNT[1:0]: Counter Select Bits
Selects a counter to be connected to the comparator/capture block of each channel in multi-comparator/
capture mode (MULTIMD/T16A_CLK0 register = 1).
8.4 Counter Selection
Table 11.
CCABCNT[1:0]
Counter channel
0x3
Ch.3 (Counter 3)
0x2
Ch.2 (Counter 2)
0x1
Ch.1 (Counter 1)
0x0
Ch.0 (Counter 0)
(Default: 0x0)
When using the T16A module in normal channel mode (T16AMULTIMD = 0), be sure to connect the
counter of the same channel to each comparator/capture block.
D3
CBUFEN: Compare Buffer Enable Bit
Enables or disables writing to the compare buffer.
1 (R/W): Enabled
0 (R/W): Disabled (default)
When CBUFEN is set to 1, compare data is written via the compare data buffer. The buffer contents are
loaded into the compare A and compare B registers when the compare B signal is generated.
When CBUFEN is set to 0, compare data is written directly to the compare A and compare B registers.
Note: Make sure the counter is halted (PRUN = 0) before setting CBUFEN.