APPENDIX A LIST OF I/O REGISTERS
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-5
Peripheral
Address
Register name
Function
16-bit PWM
timer Ch.1
(16-bit device)
0x5420
T16A_CTL1
T16A Counter Ch.1 Control Register
Controls the counter.
0x5422
T16A_TC1
T16A Counter Ch.1 Data Register
Counter data
0x5424
T16A_CCCTL1 T16A Comparator/Capture Ch.1 Control
Register
Controls the comparator/capture block and
TOUT.
0x5426
T16A_CCA1
T16A Compare/Capture Ch.1 A Data Register Compare A/capture A data
0x5428
T16A_CCB1
T16A Compare/Capture Ch.1 B Data Register Compare B/capture B data
0x542a
T16A_IEN1
T16A Compare/Capture Ch.1 Interrupt Enable
Register
Enables/disables interrupts.
0x542c
T16A_IFLG1
T16A Compare/Capture Ch.1 Interrupt Flag
Register
Displays/sets interrupt occurrence status.
16-bit PWM
timer Ch.2
(16-bit device)
0x5440
T16A_CTL2
T16A Counter Ch.2 Control Register
Controls the counter.
0x5442
T16A_TC2
T16A Counter Ch.2 Data Register
Counter data
0x5444
T16A_CCCTL2 T16A Comparator/Capture Ch.2 Control
Register
Controls the comparator/capture block and
TOUT.
0x5446
T16A_CCA2
T16A Compare/Capture Ch.2 A Data Register Compare A/capture A data
0x5448
T16A_CCB2
T16A Compare/Capture Ch.2 B Data Register Compare B/capture B data
0x544a
T16A_IEN2
T16A Compare/Capture Ch.2 Interrupt Enable
Register
Enables/disables interrupts.
0x544c
T16A_IFLG2
T16A Compare/Capture Ch.2 Interrupt Flag
Register
Displays/sets interrupt occurrence status.
16-bit PWM
timer Ch.3
(16-bit device)
0x5460
T16A_CTL3
T16A Counter Ch.3 Control Register
Controls the counter.
0x5462
T16A_TC3
T16A Counter Ch.3 Data Register
Counter data
0x5464
T16A_CCCTL3 T16A Comparator/Capture Ch.3 Control
Register
Controls the comparator/capture block and
TOUT.
0x5466
T16A_CCA3
T16A Compare/Capture Ch.3 A Data Register Compare A/capture A data
0x5468
T16A_CCB3
T16A Compare/Capture Ch.3 B Data Register Compare B/capture B data
0x546a
T16A_IEN3
T16A Compare/Capture Ch.3 Interrupt Enable
Register
Enables/disables interrupts.
0x546c
T16A_IFLG3
T16A Compare/Capture Ch.3 Interrupt Flag
Register
Displays/sets interrupt occurrence status.
Flash controller
(16-bit device)
0x54b0
FLASHC_
WAIT
FLASHC Read Wait Control Register
Sets Flash read wait cycle.
Core I/O Reserved Area (0xffff84–0xffffd0)
Peripheral
Address
Register name
Function
S1C17 Core I/O
0xffff84
IDIR
Processor ID Register
Indicates the processor ID.
0xffff90
DBRAM
Debug RAM Base Register
Indicates the debug RAM base address.
0xffffa0
DCR
Debug Control Register
Controls debugging.
0xffffb4
IBAR1
Instruction Break Address Register 1
Sets Instruction break address #1.
0xffffb8
IBAR2
Instruction Break Address Register 2
Sets Instruction break address #2.
0xffffbc
IBAR3
Instruction Break Address Register 3
Sets Instruction break address #3.
0xffffd0
IBAR4
Instruction Break Address Register 4
Sets Instruction break address #4.
Note: Addresses marked as “Reserved” or unused peripheral circuit areas not marked in the table must
not be accessed by application programs.
0x4100–0x4107, 0x506c
UART (with IrDA) Ch.0
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
UART Ch.0
Status Register
(UART_ST0)
0x4100
(8 bits)
D7
TRED
End of transmission flag
1 Completed 0 Not completed
0
R/W Reset by writing 1.
D6
FER
Framing error flag
1 Error
0 Normal
0
R/W
D5
PER
Parity error flag
1 Error
0 Normal
0
R/W
D4
OER
Overrun error flag
1 Error
0 Normal
0
R/W
D3
RD2B
Second byte receive flag
1 Ready
0 Empty
0
R
D2
TRBS
Transmit busy flag
1 Busy
0 Idle
0
R Shift register status
D1
RDRY
Receive data ready flag
1 Ready
0 Empty
0
R
D0
TDBE
Transmit data buffer empty flag
1 Empty
0 Not empty
1
R
UART Ch.0
Transmit Data
Register
(UART_TXD0)
0x4101
(8 bits)
D7–0 TXD[7:0]
Transmit data
TXD7(6) = MSB
TXD0 = LSB
0x0 to 0xff (0x7f)
0x0 R/W
UART Ch.0
Receive Data
Register
(UART_RXD0)
0x4102
(8 bits)
D7–0 RXD[7:0]
Receive data in the receive data
buffer
RXD7(6) = MSB
RXD0 = LSB
0x0 to 0xff (0x7f)
0x0
R Older data in the buf-
fer is read out first.