APPENDIX A LIST OF I/O REGISTERS
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-9
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16 Ch.1
Interrupt
Control Register
(T16_INT1)
0x4248
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
T16IE
T16 interrupt enable
1 Enable
0 Disable
0
R/W
D7–1 –
reserved
–
0 when being read.
D0
T16IF
T16 interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
0x4260–0x4268
16-bit Timer Ch.2
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16 Ch.2 Count
Clock Select
Register
(T16_CLK2)
0x4260
(16 bits)
D15–4 –
reserved
–
0 when being read.
D3–0 DF[3:0]
Count clock division ratio select
DF[3:0]
Division ratio
0x0 R/W Source clock = PCLK
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
T16 Ch.2
Reload Data
Register
(T16_TR2)
0x4262
(16 bits)
D15–0 TR[15:0]
Reload data
TR15 = MSB
TR0 = LSB
0x0 to 0xffff
0x0 R/W
T16 Ch.2
Counter Data
Register
(T16_TC2)
0x4264
(16 bits)
D15–0 TC[15:0]
Counter data
TC15 = MSB
TC0 = LSB
0x0 to 0xffff
0xffff
R
T16 Ch.2
Control Register
(T16_CTL2)
0x4266
(16 bits)
D15–5 –
reserved
–
Do not write 1.
D4
TRMD
Count mode select
1 One shot
0 Repeat
0
R/W
D3–2 –
reserved
–
0 when being read.
D1
PRESER
Timer reset
1 Reset
0 Ignored
0
W
D0
PRUN
Timer run/stop control
1 Run
0 Stop
0
R/W
T16 Ch.2
Interrupt
Control Register
(T16_INT2)
0x4268
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
T16IE
T16 interrupt enable
1 Enable
0 Disable
0
R/W
D7–1 –
reserved
–
0 when being read.
D0
T16IF
T16 interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
0x4280–0x4288
Fine Mode 16-bit Timer Ch.1
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16F Ch.1
Count Clock
Select Register
(T16F_CLK1)
0x4280
(16 bits)
D15–4 –
reserved
–
0 when being read.
D3–0 DF[3:0]
Count clock division ratio select
DF[3:0]
Division ratio
0x0 R/W Source clock = PCLK
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
T16F Ch.1
Reload Data
Register
(T16F_TR1)
0x4282
(16 bits)
D15–0 TR[15:0]
Reload data
TR15 = MSB
TR0 = LSB
0x0 to 0xffff
0x0 R/W
T16F Ch.1
Counter Data
Register
(T16F_TC1)
0x4284
(16 bits)
D15–0 TC[15:0]
Counter data
TC15 = MSB
TC0 = LSB
0x0 to 0xffff
0xffff
R