APPENDIX A LIST OF I/O REGISTERS
AP-A-12
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
I2C Slave
Control Register
(I2CS_CTL)
0x4366
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
TBUF_CLR I2CS_TRNS register clear
1 Clear state 0 Normal
0
R/W
D7
I2CSEN
I2C slave enable
1 Enable
0 Disable
0
R/W
D6
SOFTRESET Software reset
1 Reset
0 Cancel
0
R/W
D5
NAK_ANS NAK answer
1 NAK
0 ACK
0
R/W
D4
BFREQ_EN Bus free request enable
1 Enable
0 Disable
0
R/W
D3
CLKSTR_EN Clock stretch On/Off
1 On
0 Off
0
R/W
D2
NF_EN
Noise filter On/Off
1 On
0 Off
0
R/W
D1
ASDET_EN Async.address detection On/Off
1 On
0 Off
0
R/W
D0
COM_MODE I2C slave communication mode
1 Active
0 Standby
0
R/W
I2C Slave
Status Register
(I2CS_STAT)
0x4368
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7
BSTAT
Bus status transition
1 Changed
0 Unchanged
0
R
D6
–
reserved
–
0 when being read.
D5
TXUDF
Transmit data underflow
1 Occurred
0 Not occurred
0
R/W Reset by writing 1.
RXOVF
Receive data overflow
D4
BFREQ
Bus free request
1 Occurred
0 Not occurred
0
R/W
D3
DMS
Output data mismatch
1 Error
0 Normal
0
R/W
D2
ASDET
Async. address detection status
1 Detected
0 Not detected
0
R/W
D1
DA_NAK
NAK receive status
1 NAK
0 ACK
0
R/W
D0
DA_STOP
STOP condition detect
1 Detected
0 Not detected
0
R/W
I2C Slave
Access Status
Register
(I2CS_ASTAT)
0x436a
(16 bits)
D15–5 –
reserved
–
0 when being read.
D4
RXRDY
Receive data ready
1 Ready
0 Not ready
0
R
D3
TXEMP
Transmit data empty
1 Empty
0 Not empty
0
R
D2
BUSY
I2C bus status
1 Busy
0 Free
0
R
D1
SELECTED I2C slave select status
1 Selected
0 Not selected
0
R
D0
R/W
Read/write direction
1 Output
0 Input
0
R
I2C Slave
Interrupt Control
Register
(I2CS_ICTL)
0x436c
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2
BSTAT_IEN Bus status interrupt enable
1 Enable
0 Disable
0
R/W
D1
RXRDY_IEN Receive interrupt enable
1 Enable
0 Disable
0
R/W
D0
TXEMP_IEN Transmit interrupt enable
1 Enable
0 Disable
0
R/W
0x4380–0x4386
SPI Ch.1
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
SPI Ch.1
Status Register
(SPI_ST1)
0x4380
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2
SPBSY
Transfer busy flag (master)
1 Busy
0 Idle
0
R
ss signal low flag (slave)
1 ss = L
0 ss = H
D1
SPRBF
Receive data buffer full flag
1 Full
0 Not full
0
R
D0
SPTBE
Transmit data buffer empty flag
1 Empty
0 Not empty
1
R
SPI Ch.1
Transmit Data
Register
(SPI_TXD1)
0x4382
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 SPTDB[7:0] SPI transmit data buffer
SPTDB7 = MSB
SPTDB0 = LSB
0x0 to 0xff
0x0 R/W
SPI Ch.1
Receive Data
Register
(SPI_RXD1)
0x4384
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 SPRDB[7:0] SPI receive data buffer
SPRDB7 = MSB
SPRDB0 = LSB
0x0 to 0xff
0x0
R
SPI Ch.1
Control Register
(SPI_CTL1)
0x4386
(16 bits)
D15–10 –
reserved
–
0 when being read.
D9
MCLK
SPI clock source select
1 T16 Ch.1
0 PCLK/4
0
R/W
D8
MLSB
LSB/MSB first mode select
1 LSB
0 MSB
0
R/W
D7–6 –
reserved
–
0 when being read.
D5
SPRIE
Receive data buffer full int. enable 1 Enable
0 Disable
0
R/W
D4
SPTIE
Transmit data buffer empty int. enable 1 Enable
0 Disable
0
R/W
D3
CPHA
Clock phase select
1 Data out
0 Data in
0
R/W These bits must be
set before setting
SPEN to 1.
D2
CPOL
Clock polarity select
1 Active L
0 Active H
0
R/W
D1
MSSL
Master/slave mode select
1 Master
0 Slave
0
R/W
D0
SPEN
SPI enable
1 Enable
0 Disable
0
R/W
0x43a0–0x43a6
SPI Ch.2
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
SPI Ch.2 Status
Register
(SPI_ST2)
0x43a0
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2
SPBSY
Transfer busy flag (master)
1 Busy
0 Idle
0
R
ss signal low flag (slave)
1 ss = L
0 ss = H
D1
SPRBF
Receive data buffer full flag
1 Full
0 Not full
0
R
D0
SPTBE
Transmit data buffer empty flag
1 Empty
0 Not empty
1
R
SPI Ch.2
Transmit Data
Register
(SPI_TXD2)
0x43a2
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 SPTDB[7:0] SPI transmit data buffer
SPTDB7 = MSB
SPTDB0 = LSB
0x0 to 0xff
0x0 R/W