2 CPU
2-4
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Classification
Mnemonic
Function
Logical operation
and
%rd,%rs
Logical AND between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
and/c
and/nc
and
%rd,sign7
Logical AND of general-purpose register and immediate
or
%rd,%rs
Logical OR between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
or/c
or/nc
or
%rd,sign7
Logical OR of general-purpose register and immediate
xor
%rd,%rs
Exclusive OR between general-purpose registers
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
xor/c
xor/nc
xor
%rd,sign7
Exclusive OR of general-purpose register and immediate
not
%rd,%rs
Logical inversion between general-purpose registers (1's complement)
Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0).
not/c
not/nc
not
%rd,sign7
Logical inversion of general-purpose register and immediate (1's complement)
Shift and swap
sr
%rd,%rs
Logical shift to the right with the number of bits specied by the register
%rd,imm7
Logical shift to the right with the number of bits specied by immediate
sa
%rd,%rs
Arithmetic shift to the right with the number of bits specied by the register
%rd,imm7
Arithmetic shift to the right with the number of bits specied by immediate
sl
%rd,%rs
Logical shift to the left with the number of bits specied by the register
%rd,imm7
Logical shift to the left with the number of bits specied by immediate
swap
%rd,%rs
Bytewise swap on byte boundary in 16 bits
Immediate extension ext
imm13
Extend operand in the following instruction
Conversion
cv.ab
%rd,%rs
Converts signed 8-bit data into 24 bits
cv.as
%rd,%rs
Converts signed 16-bit data into 24 bits
cv.al
%rd,%rs
Converts 32-bit data into 24 bits
cv.la
%rd,%rs
Converts 24-bit data into 32 bits
cv.ls
%rd,%rs
Converts 16-bit data into 32 bits
Branch
jpr
jpr.d
sign10
PC relative jump
Delayed branching possible
%rb
jpa
jpa.d
imm7
Absolute jump
Delayed branching possible
%rb
jrgt
jrgt.d
sign7
PC relative conditional jump
Branch condition: !Z & !(N ^ V)
Delayed branching possible
jrge
jrge.d
sign7
PC relative conditional jump
Branch condition: !(N ^ V)
Delayed branching possible
jrlt
jrlt.d
sign7
PC relative conditional jump
Branch condition: N ^ V
Delayed branching possible
jrle
jrle.d
sign7
PC relative conditional jump
Branch condition: Z | N ^ V
Delayed branching possible
jrugt
jrugt.d
sign7
PC relative conditional jump
Branch condition: !Z & !C
Delayed branching possible
jruge
jruge.d
sign7
PC relative conditional jump
Branch condition: !C
Delayed branching possible
jrult
jrult.d
sign7
PC relative conditional jump
Branch condition: C
Delayed branching possible
jrule
jrule.d
sign7
PC relative conditional jump
Branch condition: Z | C
Delayed branching possible
jreq
jreq.d
sign7
PC relative conditional jump
Branch condition: Z
Delayed branching possible
jrne
jrne.d
sign7
PC relative conditional jump
Branch condition: !Z
Delayed branching possible
call
call.d
sign10
PC relative subroutine call
Delayed call possible
%rb
calla
calla.d
imm7
Absolute subroutine call
Delayed call possible
%rb
ret
ret.d
Return from subroutine
Delayed return possible
int
imm5
Software interrupt
intl
imm5,imm3
Software interrupt with interrupt level setting
reti
reti.d
Return from interrupt handling
Delayed call possible
brk
Debug interrupt