APPENDIX A LIST OF I/O REGISTERS
AP-A-34
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16A
Comparator/
Capture Ch.3
Interrupt Enable
Register
(T16A_IEN3)
0x546a
(16 bits)
D15–6 –
reserved
–
0 when being read.
D5
CAPBOWIE Capture B overwrite interrupt enable 1 Enable
0 Disable
0
R/W
D4
CAPAOWIE Capture A overwrite interrupt enable 1 Enable
0 Disable
0
R/W
D3
CAPBIE
Capture B interrupt enable
1 Enable
0 Disable
0
R/W
D2
CAPAIE
Capture A interrupt enable
1 Enable
0 Disable
0
R/W
D1
CBIE
Compare B interrupt enable
1 Enable
0 Disable
0
R/W
D0
CAIE
Compare A interrupt enable
1 Enable
0 Disable
0
R/W
T16A
Comparator/
Capture Ch.3
Interrupt Flag
Register
(T16A_IFLG3)
0x546c
(16 bits)
D15–6 –
reserved
–
0 when being read.
D5
CAPBOWIF Capture B overwrite interrupt flag 1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
D4
CAPAOWIF Capture A overwrite interrupt flag
0
R/W
D3
CAPBIF
Capture B interrupt flag
0
R/W
D2
CAPAIF
Capture A interrupt flag
0
R/W
D1
CBIF
Compare B interrupt flag
0
R/W
D0
CAIF
Compare A interrupt flag
0
R/W
0x54b0
Flash Controller
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
FLASHC Read
Wait Control
Register
(FLASHC_
WAIT)
0x54b0
(16 bits)
D15–2 –
reserved
–
0 when being read.
D1–0 RDWAIT
[1:0]
Flash read wait cycle
RDWAIT[1:0]
Wait
0x3 R/W
0x3
0x2
0x1
0x0
2 wait
1 wait
No wait
reserved
0xffff84–0xffffd0
S1C17 Core I/O
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Processor ID
Register
(IDIR)
0xffff84
(8 bits)
D7–0 IDIR[7:0]
Processor ID
0x10: S1C17 Core
0x10
R
Debug RAM
Base Register
(DBRAM)
0xffff90
(32 bits)
D31–24 –
Unused (fixed at 0)
0x0
R
D23–0 DBRAM[23:0] Debug RAM base address
0x2fc0
0x2f
c0
R
Debug Control
Register
(DCR)
0xffffa0
(8 bits)
D7
IBE4
Instruction break #4 enable
1 Enable
0 Disable
0
R/W
D6
IBE3
Instruction break #3 enable
1 Enable
0 Disable
0
R/W
D5
IBE2
Instruction break #2 enable
1 Enable
0 Disable
0
R/W
D4
DR
Debug request flag
1 Occurred
0 Not occurred
0
R/W Reset by writing 1.
D3
IBE1
Instruction break #1 enable
1 Enable
0 Disable
0
R/W
D2
IBE0
Instruction break #0 enable
1 Enable
0 Disable
0
R/W
D1
SE
Single step enable
1 Enable
0 Disable
0
R/W
D0
DM
Debug mode
1 Debug mode 0 User mode
0
R
Instruction
Break Address
Register 1
(IBAR1)
0xffffb4
(32 bits)
D31–24 –
reserved
–
0 when being read.
D23–0 IBAR1[23:0] Instruction break address #1
IBAR123 = MSB
IBAR10 = LSB
0x0 to 0xffffff
0x0 R/W
Instruction
Break Address
Register 2
(IBAR2)
0xffffb8
(32 bits)
D31–24 –
reserved
–
0 when being read.
D23–0 IBAR2[23:0] Instruction break address #2
IBAR223 = MSB
IBAR20 = LSB
0x0 to 0xffffff
0x0 R/W
Instruction
Break Address
Register 3
(IBAR3)
0xffffbc
(32 bits)
D31–24 –
reserved
–
0 when being read.
D23–0 IBAR3[23:0] Instruction break address #3
IBAR323 = MSB
IBAR30 = LSB
0x0 to 0xffffff
0x0 R/W
Instruction
Break Address
Register 4
(IBAR4)
0xffffd0
(32 bits)
D31–24 –
reserved
–
0 when being read.
D23–0 IBAR4[23:0] Instruction break address #4
IBAR423 = MSB
IBAR40 = LSB
0x0 to 0xffffff
0x0 R/W