3 MEMORY MAP, BUS CONTROL
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
3-3
Protect Bits
3.2.3
In order to protect the memory contents, the Flash memory provides two protection features, write protection and
data read protection, that can be configured for every 16K-byte areas. The write protection disables writing data to
the configured area and erasing the sectors (except the sector that includes the protect bits). The data-read protec-
tion disables reading data from the configured area (the read value is always 0x0000). However, it does not disable
the instruction fetch operation by the CPU.
The Flash memory provides the protect bits listed below. Program the protect bit corresponding to the area to be
protected to 0.
The protection can only be disabled using the debugger.
Flash Protect Bits
Address
Bit
Function
Setting
Init. R/W
Remarks
0x27ffc
(16 bits)
D15–8 reserved
–
D7
reserved
1
1 R/W Always set to 1.
D6
Flash write-protect bit for 0x20000–0x23fff
1 Writable
0 Protected
1 R/W
D5
Flash write-protect bit for 0x1c000–0x1ffff
1 Writable
0 Protected
1 R/W
D4
Flash write-protect bit for 0x18000–0x1bfff
1 Writable
0 Protected
1 R/W
D3
Flash write-protect bit for 0x14000–0x17fff
1 Writable
0 Protected
1 R/W
D2
Flash write-protect bit for 0x10000–0x13fff
1 Writable
0 Protected
1 R/W
D1
Flash write-protect bit for 0xc000–0xffff
1 Writable
0 Protected
1 R/W
D0
Flash write-protect bit for 0x8000–0xbfff
1 Writable
0 Protected
1 R/W
0x27ffe
(16 bits)
D15–8 reserved
–
D7
Flash data-read-protect bit for 0x24000–0x27fff
1 Readable
0 Protected
1 R/W
D6
Flash data-read-protect bit for 0x20000–0x23fff
1 Readable
0 Protected
1 R/W
D5
Flash data-read-protect bit for 0x1c000–0x1ffff
1 Readable
0 Protected
1 R/W
D4
Flash data-read-protect bit for 0x18000–0x1bfff
1 Readable
0 Protected
1 R/W
D3
Flash data-read-protect bit for 0x14000–0x17fff
1 Readable
0 Protected
1 R/W
D2
Flash data-read-protect bit for 0x10000–0x13fff
1 Readable
0 Protected
1 R/W
D1
Flash data-read-protect bit for 0xc000–0xffff
1 Readable
0 Protected
1 R/W
D0
reserved
1
1 R/W Always set to 1.
Notes: The protection can be disabled by erasing the sector that includes the protect bits.
Be sure not to locate the area with data-read protection into the .data and .rodata sections.
Be sure to set D0 of address 0x27ffe to 1. If it is set to 0, the program cannot be booted.
Flash Memory Read Wait Cycle Setting
3.2.4
In order to read data from the Flash memory properly, set the appropriate number of wait cycles according to the
system clock frequency using the RDWAIT[1:0]/FLASHC_WAIT register.
FLASHC Read Wait Control Register (FLASHC_WAIT)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
FLASHC Read
Wait Control
Register
(FLASHC_
WAIT)
0x54b0
(16 bits)
D15–2 –
reserved
–
0 when being read.
D1–0 RDWAIT
[1:0]
Flash read wait cycle
RDWAIT[1:0]
Wait
0x3 R/W
0x3
0x2
0x1
0x0
2 wait
1 wait
No wait
reserved
D[1:0]
RDWAIT[1:0]: Flash Read Wait Cycle Bits
Sets the number of wait cycles for reading from the Flash memory. One wait insertion prolongs bus
cycles by one system clock cycle. For the configurable wait cycles, see the “Electrical Characteristics”
chapter.
Bus cycle when “no wait” is selected
Instruction read: 1 bus cycle = 1 system clock cycle or equivalent
Data read:
1 bus cycle = 2 system clock cycles
Note: Be sure to avoid setting a number of wait cycles that exceeds the maximum allowable system
clock frequency, as it may cause a malfunction.