4 POWER SUPPLY
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
4-3
Precautions on Power Supply
4.7
Power-on sequence
In order to operate the device normally, supply power in the following sequence:
Power-on: LVDD
→ HVDD (I/O), AVDD (A/D) → Apply the input signal
or LVDD, HVDD (I/O), AVDD (A/D)
→ Apply the input signal
(See Notes in “Power-off sequence” below.)
Note: When the HVDD power is turned on from off status, stable internal circuit statuses cannot be guar-
anteed due to noise in the power line. Therefore, the circuit statuses must be initialized (reset)
after the power is turned on.
Power-off sequence
Shut off the power supply in the following sequence:
Power-off: Turn off the input signal
→ HVDD (I/O), AVDD (A/D) → LVDD
or Turn off the input signal
→ HVDD (I/O), AVDD (A/D), LVDD (See Notes below.)
Notes: Applying only LVDD with other power voltage turned off puts the HVDD system circuits into un-
stable status and unstable current flows in the I/O cells. Be sure to avoid applying only LVDD
for a duration of one second or more.
Be sure to avoid applying HVDD or AVDD for a duration of one second or more when the LVDD
power is off, as a breakdown may occur in the device or the characteristics may be degraded
due to flow-through current of the HVDD or AVDD.
Latch-up
The CMOS device may be in the latch-up condition. This is the phenomenon caused by conduction of the para-
sitic PNPN junction (thyristor) contained in the CMOS IC, resulting in a large current between HVDD and VSS
and leading to breakage.
Latch-up occurs when the voltage applied to the input / output exceeds the rated value and a large current flows
into the internal element, or when the voltage at the HVDD pin exceeds the rated value and the internal element
is in the breakdown condition. In the latter case, even if the application of a voltage exceeding the rated value is
instantaneous, the current remains high between HVDD and VSS once the device is in the latch-up condition. As
this may result in heat generation or smoking, the following points must be taken into consideration:
(1) The voltage level at the input/output must not exceed the range specified in the electrical characteristics. In
other words, it must be below the power-supply voltage and above VSS. The power-on timing should also be
taken into consideration.
(2) Abnormal noise must not be applied to the device.
(3) The potential at the unused input should be fixed at HVDD, AVDD, or VSS.
(4) No outputs should be shorted.