6 INTERRUPT CONTROLLER (ITC)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
6-3
Vector No.
Software interrupt No.
Vector address
Hardware interrupt name
Cause of hardware interrupt
Priority
14 (0x0e)
TTBR + 0x38
16-bit timer Ch.1 interrupt
Timer underow
15 (0x0f)
TTBR + 0x3c
16-bit timer Ch.2 interrupt
Timer underow
16-bit PWM timer Ch.3 interrupt
Compare A/B
Capture A/B
Capture A/B overwrite
16 (0x10)
TTBR + 0x40
UART Ch.0 interrupt
Transmit buffer empty
End of transmission
Receive buffer full
Receive error
17 (0x11)
TTBR + 0x44
UART Ch.1 interrupt
Transmit buffer empty
End of transmission
Receive buffer full
Receive error
18 (0x12)
TTBR + 0x48
SPI Ch.0 interrupt
Transmit buffer empty
Receive buffer full
19 (0x13)
TTBR + 0x4c
I2C Master interrupt
Transmit buffer empty
Receive buffer full
20 (0x14)
TTBR + 0x50
IR remote controller interrupt
Data length counter underow
Input rising edge detected
Input falling edge detected
SPI Ch.1 interrupt
Transmit buffer empty
Receive buffer full
21 (0x15)
TTBR + 0x54
16-bit PWM timer Ch.1 interrupt
Compare A/B
Capture A/B
Capture A/B overwrite
22 (0x16)
TTBR + 0x58
A/D converter interrupt
Conversion completion
Conversion result overwrite
23 (0x17)
TTBR + 0x5c
P5 port interrupt
P50–P55 port inputs
24 (0x18)
TTBR + 0x60
P2 port interrupt
P20–P27 port inputs
25 (0x19)
TTBR + 0x64
P3 port interrupt
P30–P37 port inputs
26 (0x1a)
TTBR + 0x68
I2C Slave interrupt
Transmit buffer empty
Receive buffer full
Bus status
27 (0x1b)
TTBR + 0x6c
reserved
–
:
↓
31 (0x1f)
TTBR + 0x7c
reserved
–
Low *1
*1 When the same interrupt level is set
*2 Either reset or NMI can be selected as the watchdog timer interrupt with software.
Vector numbers 4 to 26 are assigned to the maskable interrupts supported by the S1C17554/564.
Interrupts that share an interrupt vector
Interrupt vector numbers 12, 15, and 20 are shared with two different interrupt modules.
Interrupt vector 12: Fine mode 16-bit timer Ch.0/Ch.1 and USI Ch.0/Ch.1
Interrupt vector 15: 16-bit timer Ch.2 and 16-bit PWM timer Ch.3
Interrupt vector 20: IR remote controller and SPI Ch.1
The interrupt signals from the two modules are input to the ITC through an OR gate. When using the two inter-
rupts, check if which interrupt has occurred by reading the interrupt flags in both modules.
The two modules cannot be set to different interrupt level, as they use the same interrupt vector.
Vector table base address
The S1C17554/564 allows the base (starting) address of the vector table to be set using the MISC_TTBRL and
MISC_TTBRH registers. “TTBR” described in Table 6.2.1 means the value set to these registers. After an ini-
tial reset, the MISC_TTBRL and MISC_TTBRH registers are set to 0x8000. Therefore, even when the vector
table location is changed, it is necessary that at least the reset vector be written to the above address. Bits 7 to 0
in the MISC_TTBRL register are fixed at 0, so the vector table starting address always begins with a 256-byte
boundary address.