6 INTERRUPT CONTROLLER (ITC)
6-6
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
NMI
6.4
In the S1C17554/564, the watchdog timer can generate a non-maskable interrupt (NMI). The vector number for
NMI is 2, with the vector address set to the vector table's starting address + 8 bytes.
This interrupt takes precedence over other interrupts and is unconditionally accepted by the S1C17 Core.
For detailed information on generating NMI, see the “Watchdog Timer (WDT)” chapter.
Software Interrupts
6.5
The S1C17 Core provides the “int imm5” and “intl imm5,imm3” instructions allowing the software to gener-
ate any interrupts. The operand imm5 specifies a vector number (0–31) in the vector table. In addition to this, the
intl instruction has the operand imm3 to specify the interrupt level (0–7) to be set to the IL field in the PSR.
The processor performs the same interrupt processing as that of the hardware interrupt.
HALT and SLEEP Mode Cancellation
6.6
HALT and SLEEP modes are cleared by the following signals, which start the CPU.
Interrupt request signal sent to the CPU from the ITC
NMI signal output by the watchdog timer
Debug interrupt signal
Reset signal
Notes: If the CPU is able to receive interrupts when HALT or SLEEP mode has been cleared by an
interrupt request for the CPU from the ITC, processing branches to the interrupt handler rou-
tine immediately after cancellation. In all other cases, the program is executed following the
halt or slp instruction.
HALT or SLEEP mode clearing due to interrupt requests cannot be masked (prohibited) using
ITC interrupt level settings.
For more information, see “Power Saving by Clock Control” in the appendix chapter. For the oscillator circuit and
system clock statuses after HALT or SLEEP mode is canceled, see the “Clock Generator (CLG)” chapter.
Control Register Details
6.7
7.1 List of ITC Registers
Table 6.
Address
Register name
Function
0x4306
ITC_LV0
Interrupt Level Setup Register 0
Sets the P0 and P1 interrupt levels.
0x4308
ITC_LV1
Interrupt Level Setup Register 1
Sets the SWT and CT interrupt levels.
0x430a
ITC_LV2
Interrupt Level Setup Register 2
Sets the T16A Ch.2 and P4 interrupt levels.
0x430c
ITC_LV3
Interrupt Level Setup Register 3
Sets the SPI Ch.2 and T16A Ch.0 interrupt levels.
0x430e
ITC_LV4
Interrupt Level Setup Register 4
Sets the T16F Ch.0 & Ch.1/USI Ch.0 & Ch.1 and T16 Ch.0 interrupt levels.
0x4310
ITC_LV5
Interrupt Level Setup Register 5
Sets the T16 Ch.1 and T16 Ch.2/T16A Ch.3 interrupt levels.
0x4312
ITC_LV6
Interrupt Level Setup Register 6
Sets the UART Ch.0 and Ch.1 interrupt levels.
0x4314
ITC_LV7
Interrupt Level Setup Register 7
Sets the SPI Ch.0 and I2CM interrupt levels.
0x4316
ITC_LV8
Interrupt Level Setup Register 8
Sets the REMC/SPI Ch.1 and T16A Ch.1 interrupt levels.
0x4318
ITC_LV9
Interrupt Level Setup Register 9
Sets the ADC10 and P5 interrupt levels.
0x431a
ITC_LV10 Interrupt Level Setup Register 10
Sets the P2 and P3 interrupt levels.
0x431c
ITC_LV11 Interrupt Level Setup Register 11
Sets the I2CS interrupt level.
The ITC registers are described in detail below. These are 16-bit registers.
Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.