7 CLOCK GENERATOR (CLG)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
7-7
Switching the system clock to OSC1 from IOSC or OSC3
1. Disable the OSC1 oscillation stabilization wait circuit when a stabilized external clock is input to the OSC1
pin. (OSC1WCE = 0)
2. Turn the OSC1 oscillator on. (OSC1EN = 1)
3. Select the OSC1 clock as the system clock. (CLKSRC[1:0] = 0x1)
4. Turn the IOSC or OSC3 oscillator off if peripheral modules and FOUTA/B output circuits have not used the
IOSC or OSC3 clock.
Switching the system clock to IOSC from OSC3 or OSC1 (S1C17564)
1. Set the IOSC oscillation stabilization wait time if necessary. (IOSCWT[1:0])
2. Turn the IOSC oscillator on if it is off. (IOSCEN = 1)
3. Select the IOSC clock as the system clock. (CLKSRC[1:0] = 0x0)
4. Turn the OSC3 or OSC1 oscillator off if peripheral modules and FOUTA/B output circuits have not used
the OSC3 or OSC1 clock.
Notes: The oscillator to be used as the system clock source must be operated before switching
the system clock. Otherwise, the CLG will not switch the system clock source, even if CLK-
SRC[1:0] is written to, and the CLKSRC[1:0] value will remain unchanged.
The tables below list the combinations of clock operating status and register settings enabling
system clock selection.
4.2 System Clock Switching Conditions (S1C17554)
Table 7.
OSC3EN
OSC1EN
System clock
1
OSC3 or OSC1
4.3 System Clock Switching Conditions (S1C17564)
Table 7.
IOSCEN
OSC3EN
OSC1EN
System clock
1
IOSC, OSC3, or OSC1
1
0
1
IOSC or OSC1
0
1
OSC3 or OSC1
The oscillator circuit selected as the system clock source cannot be turned off.
Continuous write/read access to CLKSRC[1:0] is prohibited. At least one instruction unrelated
to CLKSRC[1:0] access must be inserted between the write and read instructions.
When SLEEP mode is canceled in the S1C17564, the IOSC oscillator circuit is turned on (IO-
SCEN = 1) and is used as the system clock source (CLKSRC[1:0] = 0x0) regardless of the
system clock configured before the chip entered SLEEP mode.
Canceling HALT mode does not change the clock status configured before the chip entered
HALT mode.
CPU Core Clock (CCLK) Control
7.5
The CLG module includes a clock gear to slow down the system clock to send to the S1C17 Core. To reduce cur-
rent consumption, operate the S1C17 Core with the slowest possible clock speed. The halt instruction can be ex-
ecuted to stop the clock supply from the CLG to the S1C17 Core for power savings.
fIOSC
fOSC3
fOSC1
CCLK
Clock gear
(1/1–1/8)
Gate
S1C17 Core
Gear selection
System clock
HALT
S1C17564
5.1 CCLK Supply System
Figure 7.