7 CLOCK GENERATOR (CLG)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
7-9
6.2 Peripheral Modules and Operating Clocks
Table 7.
Peripheral modules
Operating clock
Remarks
UART Ch.0 and 1
PCLK
The PCLK supply cannot be disabled if one or more
peripheral modules in these list must be operated.
The PCLK supply can be disabled if all the periph-
eral circuits in these list can be stopped.
Fine mode 16-bit timer
Ch.0 and 1
16-bit timer Ch.0 to 2
SPI Ch.0 to 2
USI Ch.0 and 1
(S1C17564)
I2C master
I2C slave
Power generator
(S1C17564)
P port & port MUX
MISC registers
IR remote controller
A/D converter
Clock timer
Divided OSC1 clock
The OSC1 oscillator circuit cannot be disabled if
one or more peripheral modules in these list must
be operated. The PCLK supply can be disabled.
Stopwatch timer
Watchdog timer
16-bit PWM timer
Ch.0 to 3
Clock selected by software
(divided IOSC/OSC3/OSC1 clock)
The oscillator circuit used as the clock source can-
not be disabled (see Section 7.7 or each peripheral
module chapter). The PCLK supply can be disabled.
FOUTA/FOUTB outputs
Clock External Output (FOUTA, FOUTB)
7.7
A divided IOSC/OSC3 clock or the OSC1 clock can be output to external devices.
I/O port (FOUTA pin)
Divider
(1/1–1/4)
OSC3 clock
FOUTA
output circuit
On/Off
control
Clock source
selection
On/Off
control
Clock source
selection
FOUTA division ratio selection
FOUTB division ratio selection
Divider
(1/1–1/4)
IOSC clock
OSC1 clock
I/O port (FOUTB pin)
FOUTB
output circuit
S1C17564
7.1 Clock Output Circuit
Figure 7.
There are two output systems available: FOUTA and FOUTB. The FOUTA and FOUTB output circuits have the
same functions.
Output pin setting
The FOUTA and FOUTB output pins are shared with I/O ports. The pin is configured for the I/O port by de-
fault, so the pin function should be changed using the port function select bit before the clock output can be
used. See the “I/O Ports (P)” chapter for the FOUTA/FOUTB pins and selecting pin functions.
Clock source selection
The clock source can be selected from IOSC (S1C17564), OSC3, and OSC1 using FOUTASRC[1:0]/CLG_
FOUTA register or FOUTBSRC[1:0]/CLG_FOUTB register.
7.1 Clock Source Selection
Table 7.
FOUTASRC[1:0]/
FOUTBSRC[1:0]
Clock source
S1C17554
S1C17564
0x3
Reserved
0x2
OSC3
0x1
OSC1
0x0
Reserved
IOSC
(Default: 0x0)