7 CLOCK GENERATOR (CLG)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
7-11
D[1:0]
CLKSRC[1:0]: System Clock Source Select Bits
Selects the system clock source.
8.2 System Clock Selection
Table 7.
CLKSRC[1:0]
System clock source
S1C17554
S1C17564
0x3
Reserved
0x2
OSC3 (default)
OSC3
0x1
OSC1
0x0
Reserved
IOSC (default)
Select IOSC or OSC3 for normal (high-speed) operations. If no high-speed clock is required, OSC1 can
be set as the system clock and IOSC and OSC3 stopped to reduce current consumption.
Notes: The oscillator to be used as the system clock source must be operated before switching
the system clock. Otherwise, the CLG will not switch the system clock source, even if CLK-
SRC[1:0] is written to, and the CLKSRC[1:0] value will remain unchanged.
The tables below list the combinations of clock operating status and register settings en-
abling system clock selection.
8.3 System Clock Switching Conditions (S1C17554)
Table 7.
OSC3EN
OSC1EN
System clock
1
OSC3 or OSC1
8.4 System Clock Switching Conditions (S1C17564)
Table 7.
IOSCEN
OSC3EN
OSC1EN
System clock
1
IOSC, OSC3, or OSC1
1
0
1
IOSC or OSC1
0
1
OSC3 or OSC1
The oscillator circuit selected as the system clock source cannot be turned off.
Continuous write/read access to CLKSRC[1:0] is prohibited. At least one instruction unre-
lated to CLKSRC[1:0] access must be inserted between the write and read instructions.
When SLEEP mode is canceled in the S1C17564, the IOSC oscillator circuit is turned on
(IOSCEN = 1) and is used as the system clock source (CLKSRC[1:0] = 0x0) regardless of
the system clock configured before the chip entered SLEEP mode.
Canceling HALT mode does not change the clock status configured before the chip entered
HALT mode.
Oscillation Control Register (CLG_CTL)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Oscillation
Control Register
(CLG_CTL)
S1C17554
0x5061
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–4 OSC3WT[1:0] OSC3 wait cycle select
OSC3WT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
128 cycles
256 cycles
512 cycles
1024 cycles
D3–2 –
reserved
–
0 when being read.
D1
OSC1EN
OSC1 enable
1 Enable
0 Disable
0
R/W
D0
OSC3EN
OSC3 enable
1 Enable
0 Disable
1
R/W
Oscillation
Control Register
(CLG_CTL)
S1C17564
0x5061
(8 bits)
D7–6 IOSCWT[1:0] IOSC wait cycle select
IOSCWT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
8 cycles
16 cycles
32 cycles
64 cycles
D5–4 OSC3WT[1:0] OSC3 wait cycle select
OSC3WT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
128 cycles
256 cycles
512 cycles
1024 cycles
D3
–
reserved
–
0 when being read.
D2
IOSCEN
IOSC enable
1 Enable
0 Disable
1
R/W
D1
OSC1EN
OSC1 enable
1 Enable
0 Disable
0
R/W
D0
OSC3EN
OSC3 enable
1 Enable
0 Disable
0
R/W