8 I/O PORTS (P)
8-4
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
A delay will occur in the waveform rising edge depending on time constants such as pull-up resistance and pin load
capacitance if the port pin is switched from Low level to High level through the internal pull-up resistor. An ap-
propriate wait time must be set for the I/O port loading. The wait time set should be a value not less than that calcu-
lated from the following equation.
Wait time = RIN
× (CIN + load capacitance on board) × 1.6 [s]
RIN: pull-up resistance maximum value, CIN: pin capacitance maximum value
P0–P3 Port Chattering Filter Function
8.5
The I/O ports include a chattering filter circuit for key entry that can be disabled or enabled with a check time spec-
ified individually for the four Px[3:0] and Px[7:4] ports using PxCF1[2:0]/Px_CHAT register and PxCF2[2:0]/Px_
CHAT register, respectively.
5.1 Chattering Filter Function Settings
Table 8.
PxCF1[2:0]/PxCF2[2:0]
Check time *
0x7
16384/fPCLK (8 ms)
0x6
8192/fPCLK (4 ms)
0x5
4096/fPCLK (2 ms)
0x4
2048/fPCLK (1 ms)
0x3
1024/fPCLK (512 s)
0x2
512/fPCLK (256 s)
0x1
256/fPCLK (128 s)
0x0
No check time (off)
(Default: 0x0,
* when PCLK = 2 MHz)
Notes: The chattering filter check time refers to the maximum pulse width that can be filtered.
Generating an input interrupt requires a minimum input time of the check time and a maximum
input time of twice the check time.
The Px port interrupt must be disabled before setting the Px_CHAT register. Setting the regis-
ter while the interrupt is enabled may generate inadvertent Px port interrupt. Also the chatter-
ing filter circuit requires a maximum of twice the check time for stabilizing the operation status.
Before enabling the interrupt, make sure that the stabilization time has elapsed.
Port Input Interrupt
8.6
The I/O ports include input interrupt functions.
Select which of the 40 ports are to be used for interrupts based on requirements. You can also select whether inter-
rupts are generated for either the rising edge or falling edge of the input signals.
Figure 8.6.1 shows the port input interrupt circuit configuration.
Px port
interrupt request
(to ITC)
(Px = P0 to P5)
Chattering filter
Interrupt flag
Interrupt enable
Interrupt edge selection
Px0
PxCF1[2:0]
PxEDGE0
PxIF0
PxIE0
Px7
PxCF2[2:0]
PxEDGE7
PxIF7
PxIE7
6.1 Port Input Interrupt Circuit Configuration
Figure 8.