15 UART
15-10
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Address
Register name
Function
0x4104
UART_CTL0 UART Ch.0 Control Register
Controls data transfer.
0x4105
UART_EXP0 UART Ch.0 Expansion Register
Sets IrDA mode.
0x4106
UART_BR0
UART Ch.0 Baud Rate Register
Sets baud rate.
0x4107
UART_FMD0 UART Ch.0 Fine Mode Register
Sets fine mode.
0x4120
UART_ST1
UART Ch.1 Status Register
Indicates transfer, buffer and error statuses.
0x4121
UART_TXD1 UART Ch.1 Transmit Data Register
Transmit data
0x4122
UART_RXD1 UART Ch.1 Receive Data Register
Receive data
0x4123
UART_MOD1 UART Ch.1 Mode Register
Sets transfer data format.
0x4124
UART_CTL1 UART Ch.1 Control Register
Controls data transfer.
0x4125
UART_EXP1 UART Ch.1 Expansion Register
Sets IrDA mode.
0x4126
UART_BR1
UART Ch.1 Baud Rate Register
Sets baud rate.
0x4127
UART_FMD1 UART Ch.1 Fine Mode Register
Sets fine mode.
0x506c
UART_CLK0 UART Ch.0 Clock Control Register
Selects the baud rate generator clock.
0x506d
UART_CLK1 UART Ch.1 Clock Control Register
Selects the baud rate generator clock.
The UART registers are described in detail below. These are 8-bit registers.
Notes: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
The following UART bits should be set with transfers disabled (RXEN = 0).
- All UART_MODx register bits (STPB, PMD, PREN, CHLN)
- RBFI bit in the UART_CTLx register
- All UART_EXPx register bits (IRMD)
- All UART_BRx register bits (BR[7:0])
- All UART_FMDx register bits (FMD[3:0])
- All UART_CLKx register bits (CLKDIV[1:0], CLKSRC[1:0], CLKEN)
UART Ch.x Status Registers (UART_STx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
UART Ch.x
Status Register
(UART_STx)
0x4100
0x4120
(8 bits)
D7
TRED
End of transmission flag
1 Completed 0 Not completed
0
R/W Reset by writing 1.
D6
FER
Framing error flag
1 Error
0 Normal
0
R/W
D5
PER
Parity error flag
1 Error
0 Normal
0
R/W
D4
OER
Overrun error flag
1 Error
0 Normal
0
R/W
D3
RD2B
Second byte receive flag
1 Ready
0 Empty
0
R
D2
TRBS
Transmit busy flag
1 Busy
0 Idle
0
R Shift register status
D1
RDRY
Receive data ready flag
1 Ready
0 Empty
0
R
D0
TDBE
Transmit data buffer empty flag
1 Empty
0 Not empty
1
R
D7
TRED: End of Transmission Flag Bit
Indicates whether the transmit operation has completed or not.
1 (R):
Completed
0 (R):
Not completed (default)
1 (W):
Reset to 0
0 (W):
Ignored
TRED is set to 1 when the TRBS flag is reset to 0 (when transmission has completed).
TRED is reset by writing 1.
D6
FER: Framing Error Flag Bit
Indicates whether a framing error has occurred or not.
1 (R):
Error occurred
0 (R):
No error (default)
1 (W):
Reset to 0
0 (W):
Ignored
FER is set to 1 when a framing error occurs. Framing errors occur when data is received with the stop
bit set to 0. FER is reset by writing 1.