17 I2C MASTER (I2CM)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
17-7
Clearing the cause of transmit buffer empty interrupt
Write data to RTDT[7:0]/I2CM_DAT register.
Notes: Data will not be sent if TXE/I2CM_DAT register is set to 0.
If RTDT[7:0] contains data received from the I2C bus, it will be overwritten.
Receive buffer full interrupt
To use this interrupt, set RINTE/I2CM_ICTL register to 1. If RINTE is set to 0 (default), interrupt requests for
this cause will not be sent to the ITC.
If receive buffer full interrupts are enabled (RINTE = 1), an interrupt request is output to the ITC as soon as the
data received in the shift register is loaded to RTDT[7:0].
An interrupt occurs if other interrupt conditions are met.
Checking whether a receive buffer full interrupt has occurred or not
A receive buffer full interrupt has occurred if RBUSY/I2CM_CTL register is read as 1 in the procedure
shown below.
(1) Set RINTE/I2CM_ICTL register to 1.
(2) An I2CM interrupt occurs.
(3) Read RBUSY/I2CM_CTL register.
Clearing the cause of receive buffer full interrupt
Read data from RTDT[7:0]/I2CM_DAT register.
For more information on interrupt processing, see the “Interrupt Controller (ITC)” chapter.
Control Register Details
17.7
7.1 List of I2CM Registers
Table 17.
Address
Register name
Function
0x4340
I2CM_EN
I2C Master Enable Register
Enables the I2C master module.
0x4342
I2CM_CTL
I2C Master Control Register
Controls the I2C master operation and indicates transfer status.
0x4344
I2CM_DAT
I2C Master Data Register
Transmit/receive data
0x4346
I2CM_ICTL
I2C Master Interrupt Control Register
Controls the I2C master interrupt.
The I2CM module registers are described in detail below. These are 16-bit registers.
Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.
I2C Master Enable Register (I2CM_EN)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
I2C Master En-
able Register
(I2CM_EN)
0x4340
(16 bits)
D15–1 –
reserved
–
0 when being read.
D0
I2CMEN
I2C master enable
1 Enable
0 Disable
0
R/W
D[15:1]
Reserved
D0
I2CMEN: I2C Master Enable Bit
Enables or disables I2CM module operation.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Setting I2CMEN to 1 starts the I2CM module operation, enabling data transfer. Setting I2CMEN to 0
stops the I2CM module operation.