11 16-BIT PWM TIMERS (T16A)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
11-5
When the counter reaches the value set in the compare A register during counting, the comparator asserts the
compare A signal. At the same time the compare A interrupt flag is set and the interrupt signal of the timer
channel is output to the ITC if the interrupt has been enabled.
When the counter reaches the value set in the compare B register, the comparator asserts the compare B signal.
At the same time the compare B interrupt flag is set and the interrupt signal of the timer channel is output to the
ITC if the interrupt is enabled. Furthermore, the counter is reset to 0.
The compare A period (time from start of counting to occurrence of a compare A interrupt) and the compare B
period (time from start of counting to occurrence of a compare B interrupt) can be calculated as follows:
Compare A period = (CCA + 1) / ct_clk [second]
Compare B period = (CCB + 1) / ct_clk [second]
CCA: Compare A register value set (0 to 65535)
CCB: Compare B register value set (0 to 65535)
ct_clk: Count clock frequency [Hz]
The compare A and compare B signals are also used to generate a timer output waveform (TOUT). See Section
11.6, “Timer Output Control,” for more information.
To generate PWM waveform, the T16A_CCAx and T16A_CCBx registers must be both placed into comparator
mode.
Compare buffers
Comparison data can be read or written directly from/to the compare registers. Comparison data for sys-
tem A or B can also be written to the compare buffer so that it will be loaded to the compare A or compare
B register when the compare B signal is generated. The CBUFEN/T16A_CTLx register is used to select
whether comparison data is written to the compare register or buffer.
Setting CBUFEN to 0 (default) selects the compare registers. Setting it to 1 selects the compare buffers. Al-
though the T16A_CCAx and T16A_CCBx registers are used to read/write compare data even if CBUFEN
is set to 1, compare buffers will be accessed.
Capture mode (CCAMD/CCBMD = 1)
The capture mode captures the counter value when an external event such as a key entry occurs (at the specified
edge of the external input signal). In this mode, the T16A_CCAx and/or T16A_CCBx registers function as the
capture A and/or capture B registers.
The table below lists the input pins of the external trigger signals used for capturing counter values. The pin
function of the corresponding ports must be switched for trigger input in advance. See the “I/O Ports (P)” chap-
ter for switching the pin function.
4.1.1 List of Counter Capture Trigger Signal Input Pins
Table 11.
Channel
Trigger input pins
Capture A
Capture B
T16A Ch.0
CAP0
CAP1
T16A Ch.1
CAP2
CAP3
T16A Ch.2
CAP4
CAP5
T16A Ch.3
CAP6
CAP7
The trigger edge of the signal can be selected using the CAPATRG[1:0]/T16A_CCCTLx register for capture A
and CAPBTRG[1:0]/T16A_CCCTLx register for capture B.
4.1.2 Capture Trigger Edge Selection
Table 11.
CAPATRG[1:0]/ CAPBTRG[1:0]
Trigger edge
0x3
Falling edge and rising edge
0x2
Falling edge
0x1
Rising edge
0x0
Not triggered
(Default: 0x0)
When a specified trigger edge is input during counting, the current counter value is loaded to the capture regis-
ter. At the same time the capture A or capture B interrupt flag is set and the interrupt signal of the timer channel
is output to the ITC if the interrupt has been enabled.