18 I2C SLAVE (I2CS)
18-10
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
When the clock stretch function is disabled (default)
Transmit data must be written to SDATA[7:0] within 1 cycle of the I2C clock (SCL1 input clock)
after TXEMP has been set to 1. This time is not enough for data preparation, so write transmit data
before TXEMP has been set to 1. If the previous transmit data is still stored in SDATA[7:0], it is
overwritten with the new data to be transferred. Therefore, the clear operation (see below) using
TBUF_CLR is unnecessary.
When the clock stretch function is enabled
The master device is placed into wait status by the clock stretch function, so transmit data can be
written after TXEMP is set. However, if the previous transmit data is still stored in SDATA[7:0], it
will be sent immediately after TXEMP has been set. In order to avoid this problem, clear the I2CS_
TRNS register using TBUF_CLR/I2CS_CTL register before this module is selected as the slave
device. The I2CS_TRNS register is cleared by writing 1 to TBUF_CLR then writing 0 to it.
It is not necessary to clear the I2CS_TRNS register if the first transmit data is written before TX-
EMP has been set.
I2C Slave Receive Data Register (I2CS_RECV)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
I2C Slave
Receive Data
Register
(I2CS_RECV)
0x4362
(16 bits)
D15–8 –
reserved
–
0 when being read.
D7–0 RDATA[7:0] I2C slave receive data
0–0xff
0x0
R
D[15:8]
Reserved
D[7:0]
RDATA[7:0]: I2C Slave Receive Data Bits
The received data can be read from this register. (Default: 0x0)
The serial data input from the SDA1 pin beginning with the MSB is converted into parallel data, with
the high-level signals changed to 1 and the low-level signals changed to 0. The resulting data is stored
in this register.
When a receive operation is completed and the data received in the shift register is loaded to this regis-
ter, RXRDY/I2CS_ASTAT register is set and a receive interrupt occurs. Thereafter, the data can be read
out.
When the clock stretch function has been disabled, data must be read from this register within 7 cycles
of the I2C clock (SCL1 input clock) after RXRDY is set to 1. If the next data has been received without
reading the received data, this register will be overwritten with the newly received data.
I2C Slave Address Setup Register (I2CS_SADRS)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
I2C Slave
Address Setup
Register
(I2CS_SADRS)
0x4364
(16 bits)
D15–7 –
reserved
–
0 when being read.
D6–0 SADRS[6:0] I2C slave address
0–0x7f
0x0 R/W
D[15:7]
Reserved
D[6:0]
SADRS[6:0]: I2CS Address Bits
Sets the slave address of the I2CS module to this register. (Default: 0x0)
I2C Slave Control Register (I2CS_CTL)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
I2C Slave
Control Register
(I2CS_CTL)
0x4366
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
TBUF_CLR I2CS_TRNS register clear
1 Clear state 0 Normal
0
R/W
D7
I2CSEN
I2C slave enable
1 Enable
0 Disable
0
R/W
D6
SOFTRESET Software reset
1 Reset
0 Cancel
0
R/W
D5
NAK_ANS NAK answer
1 NAK
0 ACK
0
R/W
D4
BFREQ_EN Bus free request enable
1 Enable
0 Disable
0
R/W
D3
CLKSTR_EN Clock stretch On/Off
1 On
0 Off
0
R/W
D2
NF_EN
Noise filter On/Off
1 On
0 Off
0
R/W
D1
ASDET_EN Async.address detection On/Off
1 On
0 Off
0
R/W
D0
COM_MODE I2C slave communication mode
1 Active
0 Standby
0
R/W