18 I2C SLAVE (I2CS)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
18-11
D[15:9]
Reserved
D8
TBUF_CLR: I2CS_TRNS Register Clear Bit
Clears the I2CS_TRNS register.
1 (R/W): Clear state
0 (R/W): Normal state (clear state cancellation) (default)
When TBUF_CLR is set to 1, the I2CS_TRNS register enters clear state. After that writing 0 to TBUF_
CLR returns the I2CS_TRNS register to normal state. It is not necessary to insert a waiting time be-
tween writing 1 and 0.
If a new transmission is started when the I2CS_TRNS register still stores data for the previous trans-
mission that has already finished, the data will be sent when TXEMP/I2CS_ASTAT register is set. In
order to avoid this problem, clear the I2CS_TRNS register using TBUF_CLR before starting transmis-
sion (before slave selection). The clear operation is not required if transmit data is written to the I2CS_
TRNS register before TXEMP is set to 1.
Data can be written to the I2CS_TRNS register even if it is placed into clear state (TBUF_CLR = 1).
However, this writing does not reset TXEMP to 0. Note that TXEMP is not reset to 0 when TBUF_CLR
is set back to 0. Therefore, data must be written to the I2CS_TRNS register when TBUF_CLR = 0.
D7
I2CSEN: I2C Slave Enable Bit
Enables or disables operations of the I2CS module.
1 (R/W): Enabled
0 (R/W): Disabled (default)
When I2CSEN is set to 1, the I2CS module is activated and data transfer is enabled.
When I2CSEN is set to 0, the I2CS module goes off.
D6
SOFTRESET: Software Reset Bit
Resets the I2CS module.
1 (R/W): Reset
0 (R/W): Cancel reset state (default)
To reset the I2CS module, write 1 to SOFTRESET to place the I2CS module into reset status, then
write 0 to SOFTRESET to release it from reset status. It is not necessary to insert a waiting time be-
tween writing 1 and 0. The I2CS module initializes the I2C communication process and put the SDA1
and SCL1 pins into high-impedance to be ready to detect a start condition. Furthermore, the I2CS con-
trol bits except for SOFTRESET are initialized. Perform the software reset in the initial setting process
before staring communication.
D5
NAK_ANS: NAK Answer Bit
Specifies the acknowledge bit to be sent after data reception.
1 (R/W): NAK
0 (R/W): ACK (default)
When an eight-bit data is received, the I2CS module sends back an ACK (SDA1 = low) or a NAK (SDA1
= Hi-Z). Either ACK or NAK should be specified using NAK_ANS within 7 cycles of the I2C clock
(SCL1 input clock) after RXRDY has been set to 1 by receiving the previous data.
D4
BFREQ_EN: Bus Free Request Enable Bit
Enables or disables I2C bus free requests by inputting a low pulse to the #BFR pin.
1 (R/W): Enabled
0 (R/W): Disabled (default)
To accept I2C bus free requests, set BFREQ_EN to 1. When a bus free request is accepted, BFREQ/
I2CS_STAT register is set to 1. This initializes the I2C communication process and puts the SDA1 and
SCL1 pins into high-impedance. The control registers will not be initialized in this process.
When BFREQ_EN is set to 0, low pulse inputs to the #BFR pin are ignored and BFREQ is not set to 1.