19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
19-1
Universal Serial Interface (USI)
19
[S1C17564]
Note: The universal serial interface (USI) is unavailable in the S1C17554.
USI Module Overview
19.1
The S1C17564 incorporates a two-channel universal serial interface (USI) module in which each channel can be
configured as a UART, SPI, or I2C interface unit by the software switch.
The following shows the main features of USI:
Supports four interface modes: UART, SPI master, I2C master, and I2C slave modes.
Two channels can be configured to different interface modes.
Contains one-byte receive data buffer and one-byte transmit data buffer.
Supports both MSB first and LSB first modes.
UART mode
- Character length: 7 or 8 bits
- Parity mode: even, odd, or no parity
- Stop bit: 1 or 2 bits
- Start bit: 1 bit fixed
- Parity error, framing error, and overrun error detectable
- Can generate receive buffer full, transmit buffer empty, and receive error interrupts.
SPI master mode
- Data length: 8 or 9 bits
- Supports both fast and normal modes.
- Data transfer timing (clock phase and polarity variations) is selectable from among 4 types.
- Receive data mask function is available.
- Can generate receive buffer full, transmit buffer empty, and overrun error interrupts.
I2C master/slave mode
- 7-bit addressing mode (10-bit addressing is possible by software control.)
- Supports single master configuration only (master mode).
- Supports clock stretch/wait functions.
- Can generate start/stop, data transfer, ACK/NAK transfer, and overrun error interrupts.
Figure 19.1.1 shows the USI configuration.
Shift register
Receive data
buffer (1 byte)
US_SDIx
Internal bus
ITC
USI Ch.x
Bus I/F
and
control
registers
US_SCKx
US_SSIx
Shift register
Transmit data
buffer (1 byte)
Clock/transfer control
US_SDOx
Interrupt
control
Transfer clock source
Ch.0: from T16F Ch.0
Ch.1: from T16F Ch.1
1.1 USI Configuration (one channel)
Figure 19.
Note: Two channels in the USI module have the same functions except for control register addresses.
For this reason, the description in this chapter applies to all USI channels. The ‘x’ in the register
name indicates the channel number (0 or 1).
Example: USI_GCFGx register
Ch.0: USI_GCFG0 register
Ch.1: USI_GCFG1 register