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参数资料
| 型号： | S5N8947 |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | MCU for ADSL/Cable Modem |
| 中文描述： | 单片机为ADSL / Cable Modem的 |
| 文件页数： | 11/49页 |
| 文件大小： | 407K |
| 代理商： | S5N8947 |
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ELECTRONICS
S5N8947 (ADSL/Cable Modem MCU)
SAMSUNG ELECTRONICS
Page : 11
MagIC Team
4.2. Pin Descriptions
Group
Pin Name
Pin
Counts
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
22
32
4
4
1
4
1
4
2
1
4
1
1
1
1
1
I/O
Type
I
O
I
I
I
I
O
I
O
I
I
I
I
O
I
O
I/O
O
O
O
I/O
I
O
I
O
O
I
O
O
I/O
I
Description
XCLK_I
MCLKO
CLKSEL
nRESET
CLKOEN
BIGEND
FILTER_S
OSC_XIN
OSC_XO
TMODE
TCK
TMS
TDI
TDO
nTRST
ADDR[21:0]
XDATA[31:0]
nRAS[3:0]
nCAS[3:0]
nDWE
nECS[3:0]
nDTACK
nRCS[3:0]
B0SIZE[1:0]
nOE
nWBE[3:0]
ExtMREQ
ExtMACK
MCD
MDIO
COL/COL_10M
TX_CLK/
TX_CLK_10M
TXD[3:0]/
TXD_10M/
LOOP_10M
TX_EN/
TXEN_10M
TX_ERR/
PCOMP_10M
CRS/CRS_10M
RX_CLK/
RXCLK_10M
RXD[3:0]/
RXD_10M
RX_DV/
LINK_10M
RX_ERR
UCLK
UARXD
UATXD
External System Clock Source Input.
System Clock Out.
Clock Frequency Select from the internal PLL.
System Reset, Low Active.
System Clock Out Enable.
Big endian mode select pin.
PLL filter pin for System Clock Generation.
12MHz Reference Clock.
Crystal Clock Output.
Test Mode Enable.
JTAG Test Clock Input.
JTAG Test Mode Select.
JTAG Test Data Input.
JTAG Test Data Output.
JTAG Reset Signal, Low Active.
Address Bus.
External Bidirectional 32bit Data Bus.
Row AddressSstrobe for DRAM, Low Active.
Column Address Strobe for DRAM, Low Active.
Write Enable, Low Active.
External I/O Select, Low Active.
External Data Acknowledge Signal.
ROM/SRAM/Flash Chip Select, Low Active.
Bank 0 Data Bus Size for Boot ROM.
Output Enable, Low Active.
Write Byte Enable, Low Active.
External Master Bus Request.
External Bus Acknowledge.
Management data clock.
Management data I/O.
Collision detected/Collision detected for 10M.
System
Configurations
(9)
TAP
Control
(5)
Memory
Interface
(81)
1
I
Transmit clk/Transmit clk for 10M.
4
O
Transmit data/Transmit data for 10M.
1
O
Transmit enable/Transmit enable for 10M.
1
O
Transmit error/Packet compression enable for 10M.
1
I
Carrier sense/Carrier sense for 10M.
1
I
Receive clock/Receive clock for 10M.
4
I
Receive data/Receive data for 10M.
1
I
Receive data valid.
Ethernet
Controller
(18)
1
1
1
1
I
I
I
Receive error.
External Clock Input for UART.
UART Receive Data.
UART Transmit Data.
UART
(5)
O
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|---|---|
| S5N8947X | MCU for ADSL/Cable Modem |
| S5N8950 | G.dmt ADSL Transceiver for CO and CPE |
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相关代理商/技术参数 |
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|---|---|
| S5N8947X | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:MCU for ADSL/Cable Modem |
| S5N8950 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:G.dmt ADSL Transceiver for CO and CPE |
| S5N8951 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:G.dmt ADSL Analog Front End IC |
| S5N8951X | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:G.dmt ADSL Analog Front End IC |
| S5N8952 | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:ADSL Transceiver for NIC |
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