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| 型号： | SL28505ALCT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, QCC64 |
| 封装： | 9 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, QFN-64 |
| 文件页数： | 7/28页 |
| 文件大小： | 312K |
| 代理商： | SL28505ALCT |
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SL28505
Rev 1.0 April 24, 2008
Page 15 of 28
In this mode, the user writes the desired N and M value into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the required N value.
Associated Register Bits
Prog_CPU_EN Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note that the CPU_DAF_N and M register must
contain valid values before CPU_DAF is set. Default = 0, (No
DAF).
CPU_DAF_N – There are nine bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, (0000). The allowable values for N are detailed in the
Frequency Select Table.
CPU_DAF_M – There are 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, the allowable values for M are detailed in the Frequency
Select Table.
Prog_PCI-E_EN Enable – This bit enables SRC DAF mode.
By default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note that the SRC_DAF_N register must contain valid
values before SRC_DAF is set. Default = 0, (No DAF).
SRC_DAF_N – There are nine bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, (0000). The allowable values for N are detailed in the
Frequency Select Table.
Smooth Switching
The device contains 1 smooth switch circuit that is shared by
the CPU PLL and SRC PLL. The smooth switch circuit ensures
that when the output frequency changes by overclocking, the
transition from the old frequency to the new frequency is a
slow, smooth transition containing no glitches. The rate of
change of output frequency when using the smooth switch
circuit is less than 1 MHz/0.667
s. The frequency overshoot
and undershoot is less than 2%.
The Smooth Switch circuit can be assigned as auto or manual.
In Auto mode, clock generator will assign smooth switch
automatically when the PLL does overclocking. For manual
mode, the smooth switch circuit can be assigned to either PLL
via SMBus. By default the smooth switch circuit is set to auto
mode. Either PLL can still be over-clocked when it does not
have control of the smooth switch circuit but it is not
guaranteed to transition to the new frequency without large
frequency glitches.
It is not recommended to enable over-clocking and change the
N values of both PLLs in the same SMBUS block write and use
smooth switch mechanism on spread spectrum on/off.
PD# Clarification
The CKPWRGD/PD# pin is a dual-function pin. During initial
power-up, the pin functions as CKPWRGD. Once CKPWRGD
has been sampled HIGH by the clock chip, the pin assumes
PD# functionality. The PD# pin is an asynchronous active
LOW input used to shut off all clocks cleanly prior to shutting
off power to the device. This signal is synchronized internal to
the device prior to powering down the clock synthesizer. PD#
is also an asynchronous input for powering up the system.
When PD# is asserted LOW, all clocks need to be driven to a
LOW value and held prior to turning off the VCOs and the
crystal oscillator.
PD Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
LOW. In the event that PD mode is desired as the initial
power-on state, PD must be asserted HIGH in less than 10
s
after asserting CKPWRGD.
PD#
USB, 48MHz
DOT96T
DOT96C
SRCT 100MHz
SRCC 100MHz
CPUT, 133MHz
PCI, 33 MHz
REF
CPUC, 133MHz
Figure 3. PD Assertion Timing Waveform
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相关代理商/技术参数 |
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|---|---|
| SL28506BZC | 功能描述:时钟发生器及支持产品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28506BZC-2 | 功能描述:时钟发生器及支持产品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28506BZC-2T | 功能描述:时钟发生器及支持产品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28506BZCT | 功能描述:时钟发生器及支持产品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SL28506BZI | 功能描述:时钟发生器及支持产品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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