参数资料
型号: SL28610BLC
厂商: SILICON LABORATORIES
元件分类: 时钟产生/分配
英文描述: 100 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC48
封装: 6 X 6 MM, ROHS COMPLIANT, QFN-48
文件页数: 6/23页
文件大小: 277K
代理商: SL28610BLC
SL28610
...................... DOC #: SP-AP-0078 (Rev. AA) Page 14 of 23
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable are stopped
within two to six CPU clock periods after sampled by two rising
edges of the internal CPUC clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal causes all stopped
CPU outputs to resume normal operation in a synchronous
manner. No short or stretched clock pulses are produced when
the
clock
resumes.
The
maximum
latency
from
the
deassertion to active outputs is no more than two CPU clock
cycles.
.
Note: *Differential clocks output state can be configured through Byte 19 bits 3:.0
CPU_STP#
CPUT
CPUC
Figure 4. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT Internal
Tdrive_CPU_STP#,10 ns>200 mV
CPUC Internal
Figure 5. CPU_STP# Deassertion Waveform
Table 1. Output Driver Status during PCI_STPPCI_STP# and CPU_STP#
CPU_STP# Asserted
SMBus Disabled
OE# Pins Disabled
Single-ended Clocks
Stoppable
Running
Driven low
Non stoppable
Running
Differential Clocks
Stoppable
Clock driven high
Driven Low
Clock driven high*
Clock# driven low
Clock# driven low*
Non stoppable
Running
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