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| 型号： | SN74V3650-6PEU |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| 中文描述： | 的3.3V的CMOS先入先出存储器 |
| 文件页数： | 18/50页 |
| 文件大小： | 729K |
| 代理商： | SN74V3650-6PEU |
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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024
×
36, 2048
×
36, 4096
×
36, 8192
×
36, 16384
×
36, 32768
×
36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A
–
NOVEMBER 2001
–
REVISED MARCH 2003
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
standard mode (continued)
If the FIFO is full, the first read operation causes FF to go high. Subsequent read operations cause PAF and
HF to go high at the conditions described in Table 3. If further read operations occur without write operations,
PAE goes low when there are n words in the FIFO, where n is the empty offset value. Continuing read operations
causes the FIFO to become empty. When the last word has been read from the FIFO, EF goes low, inhibiting
further read operations. REN is ignored when the FIFO is empty.
When configured in standard mode, the EF and FF outputs are register-buffered outputs.
See Figures 7, 8, 11, and 13 for timing information.
Table 2. Default Programmable Flag Offsets
SN74V3640, SN74V3650
SN74V3660, SN74V3670, SN74V3680, SN74V3690
LD
FSEL1
FSEL0
OFFSETS (n, m)
LD
FSEL1
FSEL0
OFFSETS (n, m)
L
H
L
511
H
L
L
1,023
L
L
H
255
L
H
L
511
L
L
L
127
L
L
H
255
L
H
H
63
L
L
L
127
H
L
L
31
L
H
H
63
H
H
L
15
H
H
L
31
H
L
H
7
H
L
H
15
H
H
H
3
H
H
H
7
PROGRAM MODE
Serial
Parallel
§
PROGRAM MODE
Serial
Parallel
§
H
X
X
H
X
X
L
X
X
L
X
X
n = empty offset for PAE, m = full offset for PAF
As well as selecting serial programming mode, one of the default values also is loaded, depending on the state
of FSEL0 and FSEL1.
§
As well as selecting parallel programming mode, one of the default values also is loaded, depending on the state
of FSEL0 and FSEL1.
programming flag offsets
Full and empty flag offset values are user programmable. The SN74V3640, SN74V3650, SN74V3660,
SN74V3670, SN74V3680, and SN74V3690 have internal registers for these offsets. Eight default offset values
are selectable during master reset. These offset values are shown in Table 2. Offset values can also be
programmed into the FIFO by serial or parallel loading. The loading method is selected using LD. During master
reset, the state of the LD input determines whether serial or parallel flag offset programming is enabled. A high
on LD during master reset selects serial loading of offset values. A low on LD during master reset selects parallel
loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read the current offset values. Offset values
can be read via the parallel output port Q0
–
Qn, regardless of the programming mode selected (serial or parallel).
It is not possible to read the offset values in serial fashion.
Figure 3 summarizes the control pins and sequence for both serial and parallel programming modes. A more
detailed description is given in the following paragraphs.
The offset registers may be programmed (and reprogrammed) any time after master reset, regardless of
whether serial or parallel programming has been selected. Valid programming ranges are from 0 to D
–
1.
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| SN74V3670-10PEU | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
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相关代理商/技术参数 |
参数描述 |
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| SN74V3650-7PEU | 功能描述:先进先出 2048 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V3660-10PEU | 功能描述:先进先出 4096 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V3660-15PEU | 功能描述:先进先出 4096 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V3660-6PEU | 功能描述:先进先出 4096 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| SN74V3660-7PEU | 功能描述:先进先出 4096 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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