SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024
×
36, 2048
×
36, 4096
×
36, 8192
×
36, 16384
×
36, 32768
×
36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A
–
NOVEMBER 2001
–
REVISED MARCH 2003
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
serial programming mode (continued)
Write operations to the FIFO are allowed before and during the serial programming sequence. In this case, the
programming of all offset bits need not occur at once. A select number of bits can be written to the SI input and
then, by bringing LD and SEN high, data can be written to FIFO memory via Dn by switching WEN. When WEN
is brought high with LD and SEN restored to a low, the next offset bit in sequence is written to the registers via
SI. If an interruption of serial programming is desired, it is sufficient either to set LD low and deactivate SEN,
or to set SEN low and deactivate LD. When LD and SEN are restored to a low level, serial offset programming
continues.
From the time serial programming begins, neither programmable flag is valid until the full set of bits required
to fill all the offset registers is written. Measuring from the rising WCLK edge that achieves the previous criteria,
PAF is valid after two more rising WCLK edges + t
PAF
. PAE is valid after the next two rising RCLK edges
+ t
PAE
+ t
sk2
.
Flag offset values can be read only via parallel output port Qn.
parallel programming mode
If the parallel programming mode has been selected as described previously, programming of PAE and PAF
values can be achieved by using a combination of the LD, WCLK , WEN and Dn inputs. Programming PAE and
PAF proceeds as follows. LD and WEN must be set low. For
×
36-bit input bus width, data on the inputs Dn are
written into the Empty Offset register on the first low-to-high transition of WCLK. On the second low-to-high
transition of WCLK, data are written into the Full Offset register. The third transition of WCLK writes, once again,
to the Empty Offset register. For
×
18-bit input bus width, data on the inputs Dn are written into the Empty Offset
register (LSB) on the first low-to-high transition of WCLK. On the second low-to-high transition of WCLK, data
are written into the Empty Offset (MSB) register. The third transition of WCLK writes to the Full Offset register
(LSB). The fourth transition of WCLK writes to the Full Offset register (MSB). The fifth transition of WCLK writes,
once again, to the Empty Offset register (LSB). A total of four writes to the offset registers is required to load
values using a
×
18 input bus width. For an input bus width of
×
9 bits, a total of six write cycles to the offset
registers is required to load values.
See Figures 3 and 16 for timing information.
Writing offsets in parallel employs a dedicated Write Offset register pointer. Reading offsets employs a
dedicated Read Offset register pointer. The two pointers operate independently; however, a read and a write
should not be performed simultaneously to the offset registers. A master reset initializes both pointers to the
Empty Offset register (LSB). A partial reset has no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel programming sequence. In this case,
the programming of all offset registers need not occur at one time. One, two, or more offset registers can be
written to and then, by bringing LD high, write operations can be redirected to the FIFO memory. When LD is
set low again and WEN is low, the next offset register in sequence is written to. As an alternative to holding WEN
low and switching LD, parallel programming can also be interrupted by setting LD low and switching WEN.
Note that the status of a programmable-flag (PAE or PAF) output is invalid during the programming process.
From the time parallel programming has begun, a programmable-flag output is not valid until the appropriate
offset word has been written to the register(s) pertaining to that flag. Measuring from the rising WCLK edge that
achieves the previous criteria, PAF is valid after two more rising WCLK edges + t
PAF
. PAE is valid after the next
two rising RCLK edges + t
PAE
+ t
sk2
.
Reading the offset registers employs a dedicated read offset register pointer. The contents of the offset registers
can be read on the Q0
–
Qn pins when LD is set low and REN is set low. For
×
36 output bus width, data are read
via Qn from the Empty Offset register on the first low-to-high transition of RCLK. On the second low-to-high
transition of RCLK, data are read from the Full Offset register. The third transition of RCLK reads, once again,
from the Empty Offset register. For
×
18 output bus width, a total of four read cycles is required to obtain the
values of the offset registers, starting with the Empty Offset register (LSB) and finishing with the Full Offset
register (MSB). For
×
9 output bus width, a total of six read cycles must be performed on the offset registers.