参数资料
型号: SN74V3650-6PEU
厂商: Texas Instruments, Inc.
英文描述: 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
中文描述: 的3.3V的CMOS先入先出存储器
文件页数: 3/50页
文件大小: 729K
代理商: SN74V3650-6PEU
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024
×
36, 2048
×
36, 4096
×
36, 8192
×
36, 16384
×
36, 32768
×
36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A
NOVEMBER 2001
REVISED MARCH 2003
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional block diagram
Write-Control
Logic
RAM Array
1024
×
36, 2048
×
36,
4096
×
36, 8192
×
36,
16384
×
36, 32768
×
36
Offset
Register
Input
Register
Flag
Logic
Read
Pointer
Read-Control
Logic
Output
Register
Write
Pointer
Control
Logic
Reset
Logic
BE
IP
MRS
PRS127
WEN
WCLK
D0
Dn (
×
36,
×
18, or
×
9)
SEN
HF
FWFT/SI
PFM
FSEL0
FSEL1
PAE
EF/OR
PAF
FF/IR
Q0
Qn (
×
36,
×
18, or
×
9)
OE
REN
RCLK
128
1
114
113
126
2
102
105
104
123
121
108
110
117
124
109
118
115
Bus
Configuration
IW
BM
OW
112
6
119
LD
125
RT
RM
103
107
description (continued)
The frequencies of the RCLK and WCLK signals can vary from 0 to f
MAX
, with complete independence. There
are no restrictions on the frequency of one clock input with respect to the other.
There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and
standard mode.
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three
transitions of the RCLK signal. REN need not be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a low on REN for access. The state of the FWFT/SI input during master
reset determines the timing mode.
For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode
permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a
specific read operation is performed. A read operation, which consists of activating REN and enabling a rising
RCLK edge, shifts the word from internal memory to the data output lines.
相关PDF资料
PDF描述
SN74V3660-10PEU 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3660-15PEU 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3670-10PEU 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3670-15PEU 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SN74V3690-15PEU 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
相关代理商/技术参数
参数描述
SN74V3650-7PEU 功能描述:先进先出 2048 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装:
SN74V3660-10PEU 功能描述:先进先出 4096 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装:
SN74V3660-15PEU 功能描述:先进先出 4096 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装:
SN74V3660-6PEU 功能描述:先进先出 4096 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装:
SN74V3660-7PEU 功能描述:先进先出 4096 x 36 Synch 先进先出 Memory RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: