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| 型号： | ST62T53CM6 |
| 英文描述： | 8-BIT MICROCONTROLLER ( MCU ) WITH OTP. ROM. FASTROM. EPROM. A/D CONVERTER. SAFE RESET. AUTO-RELOAD TIMER. EEPROM AND SPI |
| 中文描述： | 8位微控制器（MCU）的与检察官办公室。光盘。 FASTROM。存储器。的A / D转换器。安全复位。自动重加载定时器。的EEPROM和SPI |
| 文件页数： | 55/84页 |
| 文件大小： | 918K |
| 代理商： | ST62T53CM6 |
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ST62T53C/T60C/T63C ST62E60C
SERIAL PERIPHERAL INTERFACE SPI
(Cont’d)
4.5.1 SPI Registers
SPI Mode Control Register (MOD)
Address: E2h
—
Read/Write
Reset status: 00h
The MOD register defines and controls the trans-
mission modes and characteristics.
This register is read/write and all bits are cleared
at reset. Setting SPSTRT = 1 and SPIN = 1 is not
allowed and must be avoided.
Bit 7 =
SPRUN
:
SPI Run
. This bit is the SPI activity
flag. This can be used in either transmit or receive
modes; it is automatically cleared by the SPI at the
end of a transmission or reception and generates
an interrupt request (providing that the SPIE Inter-
rupt Enable bit is set). The Core can stop transmis-
sion or reception at any time by resetting the
SPRUN bit; this will also generate an interrupt re-
quest (providing that the SPIE Interrupt enable bit
is set). The SPRUN bit can be used as a start con-
dition parameter, in conjunction with the SPSTRT
bit, when an external signal is present on the Sin
pin. Note that a rising edge is then necessary to in-
itiate reception; this may require external data in-
version. This bit can be used to poll the end of re-
ception or transmission.
Bit 6 =
SPIE
:
SPI Interrupt Enable
. This bit is the
SPI Interrupt Enable bit. If this bit is set the SPI in-
terrupt (vector #2) is enabled, when SPIE is reset,
the interrupt is disabled.
Bit 5 =
CPHA
:
Clock Phase Selection
. This bit se-
lects the clock phase of the clock signal. If this bit
is cleared to zero the normal state is selected; in
this case Bit 7 of the data frame is present on Sout
pin as soon as the SPI Shift Register is loaded. If
this bit is set to one the shifted state' is selected; in
this case Bit 7 of data frame is present on Sout pin
on the first falling edge of Shift Register clock. The
polarity relation and the division ratio between
Shift Register and SPI base clock are also pro-
grammable; refer to DIV register and Timing Dia-
grams for more information.
Bit 4=
SPCLK
:
Base Clock Selection
This bit selects the SPI base clock source. It is ei-
ther the core cycle clock (f
INT
/13) (Master mode)
or the signal provided at SCK pin by an external
device (slave mode). If SPCLK is low and the SCK
pin is configured as input, the slave mode is se-
lected. If SPCLK is high, the SCK pin is automatic-
cally configured as push pull output and the mas-
ter mode is selected. In this case, the phase and
polarity of the clock are controlled by CPOL and
CPHA.
Note
: When the master mode is enabled, it is
mandatory to configure PC4 in input mode through
the i/o port registers.
Bit 3 =
SPIN
:
Input Selection
This bit enables the transfer of the data input to the
Shift Register in receive mode. If this bit is cleared
the Shift Register input is 0. If this bit is set, the
Shift Register input corresponds to the input signal
present on the Sin pin.
Bit 2 =
SPSTRT
:
Start Selection
This bit selects the transmission or reception start
mode. If SPSTRT is cleared, the internal start con-
dition occurs as soon as the SPRUN bit is set. If
SPSTRT is set, the internal start signal is the logic
“AND” between the SPRUN bit and the external
signal present on the Sin pin; in this case transmis-
sion will start after the latest of both signals provid-
ing that the first signal is still present (note that this
implies a rising edge). After the transmission or re-
cetion has been started, it will continue even if the
Sin signal is reset.
Bit 1 =
EFILT
:
Enable Filters
This bit enables/disables the input noise filters on
the Sin and SCK inputs. If it is cleared to zero the
filters are enabled, if set to one the filters are disa-
bled. These noise filters will eliminate any pulse on
Sin and SCK with a pulse width smaller than one
to two Core clock periods (depending on the oc-
currence of the signal edge with respect to the
Core clock edge). For example, if the ST6260B/
65B runs with an 8MHz crystal, Sin and SCK will
be delayed by 125 to 250ns.
Bit 0 =
CPOL
:
Clock Polarity
This bit controls the relationship between the data
on the Sin and Sout pins and SCK. The CPOL bit
selects the clock edge which captures data and al-
lows it to change state. It has the greatest impact
on the first bit transmitted (the MSB) as it does (or
does not) allow a clock transition before the first
data capture edge.
Refer to the timing diagrams at the end of this sec-
tion for additional details. These show the relation-
ship between CPOL, CPHA and SCK, and indicate
the active clock edges and strobe times.
7
0
SPRUN
SPIE
CPHA
SPCLK
SPIN
SPSTRT
EFILT
CPOL
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST62T55CB6 | 功能描述:8位微控制器 -MCU OTP EPROM 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST62T55CM6 | 功能描述:8位微控制器 -MCU OTP EPROM 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST62T55CM6/TR | 制造商:STMicroelectronics 功能描述: |
| ST62T55CN6 | 功能描述:8位微控制器 -MCU OTP EPROM 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST62T60BB6 | 功能描述:8位微控制器 -MCU OTP 4K W/ROM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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