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8-BIT & 12-BIT PROGRAMMABLE PULSE GENERATORS
(SERIES 3D3608 & 3D3612: PARALLEL INTERFACE)
datadelaydevICes, inc.?3
FEATURES PACKAGES / PINOUTS
12 3 4 5 6 7 8 9 10 20191817161514131211TRIG RES P0 P2 P4 P6 P8 NC P10 GND VDDOUT OUTBP1 P3 P5 P7 P9 AE P11 3D3612W-xx SOL 12 3 4 5 6 7 8 161514131211109TRIGRESP0P2P4P6NCGNDVDD OUT OUTB P1 P3 P5 P7 AE 3D3608R-xx SOIC
? All-silicon, low-power CMOS technology
? 3.3V operation
? Vapor phase, IR and wave solderable
? Programmable via latched parallel interface
? Increment range: 0.25ns through 800us
? Pulse width tolerance: 1% (See Table 1)
? Supply current: 8mA typical
For mechanical dimensions, click here.
For package marking details, click here.
? Temperature stability: ±1.5% max (-40C to 85C)
? Vdd stability: ±1.0% max (3.0V to 3.6V)
FUNCTIONAL DESCRIPTION
The 3D3608 & 3D3612 devices are versatile 8- & 12-bit programmable monolithic pulse generators. A rising-edge on the trigger input (TRIG) initiates the pulse, which is presented on the output pins (OUT,OUTB). The pulse width, programmed via the parallel interface, can be varied over 255 (3D3608) or 4095 (3D3612) equal steps according to the formula:
tPW = tinh + addr * tinc
where addr is the programmed address, tinc is the pulse width increment (equal to the device dash number), and tinh is the inherent (address zero) pulse width. The device also offers a reset input (RES), which can be used to terminate the pulse before the programmed time has expired.
PIN DESCRIPTIONS
TRIG Trigger Input
RES Reset Input
OUT Pulse Output
OUTB Complementary
Pulse Output
AE Address Enable Input
P0-P11 Address Inputs
VDD +3.3 Volts
GND Ground
NC Do not connect externally
The all-CMOS 3D3608 & 3D3612 integrated circuits have been designed as reliable, economic alternatives to hybrid TTL pulse generators. The 3D3608 is offered in a standard 16-pin SOIC, and the 3D3612 is offered in a standard 20-pin SOL.
TABLE 1: PART NUMBER SPECIFICATIONS
NOTE: Any increment between 0.25ns and 800us (50us for the 12-bit generator) not shown is also available as a standard device.
PART #
(8-BIT)
PART #
(12-BIT)
Pulse Width
Increment
Maximum
P.W. (8-Bit)
Maximum
P.W. (12-Bit)
PART #
(8-BIT)
Pulse Width
Increment
Maximum
P.W. (8-Bit)
3D3608R-0.25
3D3612W-0.25
0.25ns ± 0.12ns
78.25ns ± 3ns
1.04us ± 10ns
3D3608R-100K
100us ± 50us
25.5ms ± 260us
3D3608R-0.5
3D3612W-0.5
0.50ns ± 0.25ns
142.5ns ± 3ns
2.06us ± 21ns
3D3608R-200K
200us ± 100us
51.0ms ± 510us
3D3608R-1
3D3612W-1
1.0ns ± 0.5ns
270ns ± 3ns
4.11us ± 41ns
3D3608R-500K
500us ± 250us
128ms ± 1.3ms
3D3608R-2
3D3612W-2
2.0ns ± 1.0ns
525ns ± 6ns
8.19us ± 82ns
3D3608R-750K
750us ± 375us
191ms ± 1.9ms
3D3608R-5
3D3612W-5
5.0ns ± 2.5ns
1.28us ± 13ns
20.5us ± 205ns
3D3608R-10
3D3612W-10
10ns ± 5.0ns
2.56us ± 26ns
41.0us ± 410ns
3D3608R-20
3D3612W-20
20ns ± 10ns
5.11us ± 52ns
81.9us ± 819ns
3D3608R-50
3D3612W-50
50ns ± 25ns
12.8us ± 128ns
205us ± 2.1us
3D3608R-100
3D3612W-100
100ns ± 50ns
25.5us ± 255ns
410us ± 4.1us
3D3608R-200
3D3612W-200
200ns ± 100ns
51.0us ± 510ns
819us ± 8.2us
3D3608R-500
3D3612W-500
500ns ± 250ns
128us ± 1.3us
2.05ms ± 21us
3D3608R-1K
3D3612W-1K
1.0us ± 0.5us
255us ± 2.6us
4.10ms ± 41us
3D3608R-2K
3D3612W-2K
2.0us ± 1.0us
510us ± 5.2us
8.19ms ± 82us
3D3608R-5K
3D3612W-5K
5.0us ± 2.5us
1.28ms ± 13us
20.5ms ± 205us
3D3608R-10K
3D3612W-10K
10us ± 5.0us
2.55ms ± 26us
41.0ms ± 410us
3D3608R-20K
3D3612W-20K
20us ± 10us
5.10ms ± 52us
81.9ms ± 819us
3D3608R-50K
3D3612W-50K
50us ± 25us
12.8ms ± 128us
205ms ± 2.1 ms
?2008 Data Delay Devices
Doc #06010 DATA DELAY DEVICES, INC. 1
7/28/2008 3 Mt. Prospect Ave. Clifton, NJ 07013
3D3608 & 3D3612
APPLICATION NOTES
GENERAL INFORMATION
Figure 1 illustrates the main functional BLOCKs of the 3D3608 & 3D3612. Since these devices are CMOS designs, all unused input pins must be returned to well-defined logic levels, VDD or Ground.
The pulse generator architecture is comprised of a number of delay cells (for fine control) and an oscillator & counter (for coarse control). Each device is individually trimmed for maximum accuracy and linearity throughout the address range. The change in pulse width from one address setting to the next is calLED the increment, or LSB. It is nominally equal to the device dash number. The minimum pulse width, achieved by setting the address to zero, is called the inherent pulse width.
For best performance, it is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. Also, signal traces should be kept as short as possible.
PULSE WIDTH ACCURACY
There are a number of ways of characterizing the pulse width accuracy of a programmable pulse generator. The first is the differential nonlinearity (DNL), also referred to as the increment error. It is defined as the deviation of the increment at a given address from its nominal value. For most dash numbers, the DNL is within 0.5 LSB at every address (see Table 1: Pulse Width Step).
The integrated nonlinearity (INL) is determined by first constructing the least-squares best fit straight line through the pulse-width-versus-address data. The INL is then the deviation of a given width from this line. For all dash numbers, the INL is within 1.0 LSB at every address.
The relative error is defined as follows:
erel = (tPW – tinh) – addr * tinc
where addr is the address, tPW is the measured width at this address, tinh is the measured inherent width, and tinc is the nominal increment. It is very similar to the INL, but simpler to calculate. For most dash numbers, the relative error is less than 1.0 LSB at every address (see Table 1).
The absolute error is defined as follows:
eabs = tPW – (tinh + addr * tinc)
where tinh is the nominal inherent delay. The absolute error is limited to 1.5 LSB or 3.0 ns, whichever is greater, at every address.
The inherent pulse width error is the deviation of the inherent width from its nominal value. It is limited to 2.0 ns from the nominal inherent pulse width of 15 ns.
PULSE WIDTH STABILITY
The characteristics of CMOS integrated circuits are strongly dependent on power supply and temperature. The 3D3608 & 3D3612 utilize novel compensation circuitry to minimize the performance variations induced by fluctuations in power supply and/or temperature.
With regard to stability, the output pulse width of the 3D3608 & 3D3612 at a given address, addr, can be split into two components: the inherent pulse width (tinh) and the relative pulse width (tPW - tinh). These components exhibit very different stability coefficients, both of which must be considered in very critical applications.
The thermal coefficient of the relative pulse width is limited to ±250 PPM/C (except for the -0.25), which is equivalent to a variation, over the -40C to 85C operating range, of ±1.5% (±9% for the dash 0.25) from the room-temperature pulse width. This holds for all dash numbers. The thermal coefficient of the inherent pulse width is nominally +20ps/C for dash numbers less than 5, and +30ps/C for all other dash numbers.
The power supply sensitivity of the relative pulse width is ±1.0% (±3.0% for the dash 0.25) over the 3.0V to 3.6V operating range, with respect to the pulse width at the nominal 3.3V power supply. This holds for all dash numbers. The sensitivity of the inherent pulse width is nominally -5ps/mV for all dash numbers.
It should also be noted that the DNL is also adversely affected by thermal and supply variations, particularly at the MSL/LSB crossovers (ie, 63 to 64, 127 to 128, etc).