256Mb Synchronous DRAM(16M x 16) FEATURES
● Standard SDRAM Protocol
● Internal 4bank operation
● Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V
● All device pins are compatible with LVTTL interface
● Low Voltage interface to reduce I/O power
● 8,192 Refresh cycles / 64ms
● Programmable CAS latency of 2 or 3
● Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
● 0
o
C ~ 70
o
C Operation
● Package Type : 54_Pin TSOPII (Lead Free, Lead)
HY57V561620F(L)TP Series : Lead Free
HY57V561620F(L)T Series : Leaded
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深圳斯普仑科技有限公司
Shenzhen Spring Technology Co.,Ltd
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