以下是,AD9888KSZ-205,型号:AD9888KSZ-205 厂家:AD 封装:QFP-128 ,请点击“询价”
-AD9888KSZ-205 型号:AD9888KSZ-205 厂家:AD 封装:QFP-128-买卖IC网
AD9888KSZ-205
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,AD9888KSZ-205

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  • 发 货 期: 7 天内发货
  • 所 在 地: 广东 深圳市 福田区
  • 发布日期: 2014年04月14日
深圳斯普仑科技有限公司进入企业网站查看联系方式
  • 联系人:成先生 (先生) QQ 2853736351MSN:szspl@msn.cn
  • 电话:0755-83521389/13306526089
  • 传真:0755-83502530
  • 邮件:2433941092@qq.com
  • 地址:深圳市福田区振华路122号海外装饰大厦A座211室
型号AD9888KSZ-205厂家AD
封装QFP-128  
FEATURES 
170 MSPS maximum conversion rate 
500 MHz programmable analog bandwidth 
0.5 V to 1.0 V analog input range 
Less than 450 ps p-p PLL clock jitter at 170 MSPS 
3.3 V power supply 
Full sync processing 
Sync detect for hot plugging 
2:1 analog input mux 
4:2:2 output format mode 
Midscale clamping 
Power-down mode 
Low power: <1 W typICal at 170 MSPS 
APPLICATIONS 
RGB graphics processing 
LCD monitors and projectors 
Plasma display panels 
Scan converters 
Microdisplays 
Digital TV 
GENERAL DESCRIPTION The AD9888 is a complete 8-bit, 170 MSPS, monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 170 MSPS encode rate capability and full-power analog bandwidth of 500 MHz supports resolutions of up to 1600 × 1200 (UXGA) at 75 Hz. For ease of design and to minimize cost, the AD9888 is a fully integrated interface solution for flat panel displays. The AD9888 includes an analog interface that has a 170 MHz triple ADC with an internal 1.25 V reference phase-locked loop (PLL) to generate a pixel clock from HSYNC and COAST; midscale clamping; and programmable gain, offset, and clamp controls. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V. The on-chip PLL of the AD9888 generates a pixel clock from the HSYNC and COAST inputs. Pixel clock output frequencies range from 10 MHz to 170 MHz. PLL clock jitter is typically less than 450 ps p-p at 170 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC, and clock output phase relationships are maintained. The PLL can be disabLED, and an external clock input can be provided as the pixel clock. The AD9888 also offers full sync processing for composite sync and sync-on-green applications. A CLAMP signal is generated internally or can be provided by the user through the CLAMP input pin. This device is fully programmable via a 2-wire serial port. Fabricated in an advanced CMOS process, the AD9888 is provided in a space-saving, 128-lead, MQFP, surface-mount, plastic package and is specified over the 0°C to 70°C temperature range. The AD9888 is also available in a Pb-free package.
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