The PM73487 622 Mbps ATM TraffIC Management Device (QRT?) is an advanced communications device capable of supporting very large, high-performance ATM switching systems. The

rich feature set of the QRT enables systems to offer many sophisticated network services. The

QRT provides 622 Mbps UTOPIA (Level 1 or Level 2) access to switch fabrics composed of

PM73488 5 Gbps ATM Switch Fabric Elements (QSEs). Together, these devices can be used to

build architectures with capacities from 622 Mbps to 160 Gbps. The QRT can also act as a standalone 622 Mbps switch.

The QRT/QSE architecture virtually eliminates head-of-line BLOCKing by means of the QRT’s perVirtual Channel (VC) receive queues and congestion feedback from the QSE? switch fabric. The

distributed architecture acts as an output-buffered switch by incorporating Evil Twin Switching?

(a congestion-reducing routing algorithm in the switch fabric) and a speed-up factor in the switch

fabric (running the fabric faster than the line rate).

The QRT uses per-VC receive queues, 64 receive Service Classes (SCs), and 16 transmit SCs per

each of the 31 Virtual Outputs (VOs) to enable flexible multi-priority scheduling algorithms. The

scheduler can be used to ensure Quality-of-Service (QoS) guarantees for Constant Bit Rate

(CBR), Variable Bit Rate (VBR), and Unspecified Bit Rate (UBR) VCs. The QRT also provides

five separate congestion thresholds, each with hysteresis, that selectively control AAL5 Early

Packet Discard (EPD) and/or Cell Loss Priority (CLP)-based cell dropping for UBR support.

Additional highlights of the QRT include full Virtual Path Indicator (VPI)/Virtual Channel Indicator (VCI) header translation, separate input and output cell buffers (up to 64K each), Virtual

Path (VP)/VC switching, and support for up to 16K VCs on both the receive and transmit sides. 

PMC-Sierra also offers the QRT Device Control Package, which is a software package that harnesses the QRT’s rich feature set and shortens system development times.

FEATURES QUEUING ALGORITHMS Receive ? Maintains 64 weighted, bandwidth-controlLED SCs with per-VC queues. ? Provides round-robin servicing of queues within each SC. ? Provides per-channel (VP or VC), per-SC, and per-direction congested and maximum queue depth limits. ? Provides up to 64K cell buffers. Transmit ? Provides 31 VOs. ? Maintains 16 SCs for each VO with per-VC accounting.

? Provides per-channel (VP or VC), per-SC Queue (SCQ), per-SC, per-VO, and perdirection congested and maximum queue depth limits. ? Provides up to 64K cell buffers. CONGESTION MANAGEMENT ALGORITHMS ? Supports EPD and Partial Packet Discard (PPD) for UBR traffic, and as a backup for ABR traffic. ? Supports CLP-based cell discard and Explicit Forward Congestion Indicator (EFCI) cell marking. ? Supports three congestion limits (as well as EPD, CLP, and EFCI, and/or backpressure) for logical multicast on the transmit side. SWITCHING ? Supports VC and VP switching. ? Supports up to 16K VCs. ADDRESS MAPPING ? Supports all 12 VP and 16 VC bits through use of a double, indirect lookup table. ? Performs header translation at both the input (receive) and output (transmit) directions. Input header translation is used to pass the output queue channel number through the switch. MULTICAST ? Supports logical multicast with a superior queue-clearing algorithm. DIAGNOSTIC/ROBUSTNESS FEATURES ? Checks the header parity. ? Counts tagged cells. ? Runs error checks continually on all fabric lines. ? Checks liveness of control signal lines at both switch fabric and UTOPIA interfaces, working around partial fabric failures. ? Checks Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) parity. STATISTICS FEATURES ? In the receive direction, counts cells transmitted and dropped. ? In the transmit direction, counts cells transmitted and dropped on a per-VC basis. I/O FEATURES ? Provides four switch element interfaces with phase aligners. The phase aligners allow for external serialization of the data stream enabling systems to be built that support device separation of up to 10 meters. ? Provides a UTOPIA Level 2 Multi-PHY (MPHY) 16-bit, 50 MHz interface. ? Provides a 2-level priority servicing algorithm for high and low bandwidth UTOPIA PHY layer devices. ? Provides a multiplexed address/data CPU interface.

? Provides two 100 MHz, 32-bit, synchronous DRAM cell buffer interfaces. ? Provides three 100 MHz, synchronous SRAM control interfaces. ? Provides a JTAG boundary scan interface. COMPATIBILITY FEATURES ? Compatible with the ATM Forum 3.0, 3.1, and 4.0 specifications. ? Compatible with the ATM Forum UTOPIA Level 1 and Level 2 specifications. ? Compatible with the PM73488 ATM QSE. PHYSICAL CHARACTERISTICS ? 3.3 V supply voltage. ? 5 V tolerant inputs on the microprocessor and UTOPIA interfaces. ? Available in a 503-pin Enhanced Plastic Ball Grid Array (EPBGA) package.

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