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参数资料
| 型号： | TC850ILW |
| 元件分类： | ADC |
| 英文描述： | 1-CH 15-BIT MULTI-SLOPE ADC, PARALLEL ACCESS, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 21/26页 |
| 文件大小： | 417K |
| 代理商： | TC850ILW |
TC850
DS21479C-page 4
2006 Microchip Technology Inc.
CIN
Input Capacitance
—
1
—
pF
Pins 1 - 7, 17
COUT
Output Capacitance
—
15
—
pF
Pins 8 -15, High-impedance State
TCE
Chip-Enable Access Time
—
230
450
nsec
CS or CE, RD = LOW (Note 1)
TRE
Read-Enable Access Time
—
190
450
nsec
CS = HIGH, CE = LOW, (Note 1)
TDHC
Data Hold From CS or CE
—
250
450
nsec
RD = LOW, (Note 1)
TDHR
Data Hold From RD
—
210
450
nsec
CS = HIGH, CE = LOW, (Note 1)
TOP
OVR/POL Data Access Time
—
140
300
nsec
CS = HIGH, CE = LOW,
RD = LOW, (Note 1)
TLH
Low/High Byte Access Time
—
140
300
nsec
CS = HIGH, CE = LOW,
RD = LOW, (Note 1)
Clock Setup Time
100
—
nsec
Positive or Negative Pulse Width
TWRE
RD Minimum Pulse Width
450
230
—
nsec
CS = HIGH, CE = LOW, (Note 2)
TWRD
RD Minimum Delay Time
150
50
—
nsec
CS = HIGH, CE = LOW, (Note 2)
TWWD
WR Minimum Pulse Width
75
25
—
nsec
CS = HIGH, CE = LOW, (Note 1)
TABLE 1-1:
TC850 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: VS = ±5V; FCLK = 61.44kHz, VFS = 3.2768V, TA = 25°C, Figure 1-1, unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
Note
1:
Demand mode, CONT/DEMAND = LOW. Figure 8-2 timing diagram. CL = 100 pF.
2: Continuous mode, CONT/DEMAND = HIGH. Figure 8-4 timing diagram.
3: Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TTL compatibility, external pull-up
resistors to VDD are recommended.
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