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参数资料
型号： TMDXCNCD28069ISO
厂商： Texas Instruments
文件页数： 17/174页
文件大小： 0K
描述： EVAL PICCOLO CONTROLCARD
标准包装： 1
系列： TMS320F2806x, Piccolo™, C2000™
主要目的： 接口，RS232，GPIO
嵌入式： 是，MCU，32 位
已用 IC / 零件： TMS320F2806x
已供物品： 板
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
Table 5-37. McBSP Switching Characteristics(1)(2)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
UNIT
M1
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
2P
ns
M2
tw(CKRXH)
Pulse duration, CLKR/X high
CLKR/X int
D – 5(3)
D + 5(3)
ns
M3
tw(CKRXL)
Pulse duration, CLKR/X low
CLKR/X int
C – 5(3)
C + 5(3)
ns
M4
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
CLKR int
0
4
ns
CLKR ext
3
27
M5
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int
0
4
ns
CLKX ext
3
27
M6
tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance
CLKX int
8
ns
following last data bit
CLKX ext
14
M7
td(CKXH-DXV)
Delay time, CLKX high to DX valid.
CLKX int
9
ns
This applies to all bits except the first bit transmitted.
CLKX ext
28
Delay time, CLKX high to DX valid
DXENA = 0
CLKX int
8
CLKX ext
14
Only applies to first bit transmitted when
DXENA = 1
CLKX int
P + 8
in Data Delay 1 or 2 (XDATDLY=01b or
CLKX ext
P + 14
10b) modes
M8
ten(CKXH-DX)
Enable time, CLKX high to DX driven
DXENA = 0
CLKX int
0
ns
CLKX ext
6
Only applies to first bit transmitted when
DXENA = 1
CLKX int
P
in Data Delay 1 or 2 (XDATDLY=01b or
CLKX ext
P + 6
10b) modes
M9
td(FXH-DXV)
Delay time, FSX high to DX valid
DXENA = 0
FSX int
8
ns
FSX ext
14
Only applies to first bit transmitted when
DXENA = 1
FSX int
P + 8
in Data Delay 0 (XDATDLY=00b) mode.
FSX ext
P + 14
M10
ten(FXH-DX)
Enable time, FSX high to DX driven
DXENA = 0
FSX int
0
ns
FSX ext
6
Only applies to first bit transmitted when
DXENA = 1
FSX int
P
in Data Delay 0 (XDATDLY=00b) mode
FSX ext
P + 6
(1)
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2)
2P = 1/CLKG in ns.
(3)
C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
Copyright 2010–2012, Texas Instruments Incorporated
Peripheral and Electrical Specifications
113
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Product Folder Links: TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065
TMS320F28064 TMS320F28063 TMS320F28062
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