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7.5 Interrupts
7.5.1
Interrupt Sources and Interrupt Controller
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A–APRIL 2006–REVISED DECEMBER 2006
The CPU interrupts on the C6454 device are configured through the C64x+ Megamodule Interrupt
Controller. The interrupt controller allows for up to 128 system events to be programmed to any of the
twelve CPU interrupt inputs, the CPU exception input, or the advanced emulation logic. Table 8-4 shows
the mapping of system events to the interrupt controller inputs. Event numbers 0-31 correspond to the
default interrupt mapping of the device. The remaining events must be mapped using software.
For more information on the Interrupt Controller, see the
TMS320C64x+ Megamodule Reference Guide
(literature number
SPRU871
).
Table 7-10. C6454 DSP Interrupts
EVENT NUMBER
0
(1)
1
(1)
2
(1)
3
(1)
4 - 8
(2)
INTERRUPT EVENT
EVT0
EVT1
EVT2
EVT3
Reserved
INTERRUPT SOURCE
Interrupt Controller output of event combiner 0, for events 1 - 31.
Interrupt Controller output of event combiner 1, for events 32 - 63.
Interrupt Controller output of event combiner 2, for events 64 - 95.
Interrupt Controller output of event combiner 3, for events 96 - 127.
Reserved. Do not use.
EMU interrupt for:
1.
Host scan access
2.
DTDMA transfer complete
3.
AET interrupt
Reserved. Do not use.
EMU real-time data exchange (RTDX) receive complete
EMU RTDX transmit complete
IDMA channel 0 interrupt
IDMA channel 1 interrupt
HPI/PCI-to-DSP interrupt
I2C interrupt
Ethernet MAC interrupt
EMIFA error interrupt
Reserved. Do not use.
EDMA3 channel global completion interrupt
Reserved. Do not use.
McBSP0 receive interrupt
McBSP0 transmit interrupt
McBSP1 receive interrupt
McBSP1 transmit interrupt
Reserved. Do not use.
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
9
(2)
EMU_DTDMA
10
(2)
11
(2)
12
(2)
13
(2)
14
(2)
15
(2)
16
17
18
19 - 23
24
25 - 39
40
41
42
43
44 - 50
51
52
53
54
55
56
57
58
Reserved
EMU_RTDXRX
EMU_RTDXTX
IDMA0
IDMA1
DSPINT
I2CINT
MACINT
AEASYNCERR
Reserved
EDMA3CC_GINT
Reserved
RINT0
XINT0
RINT1
XINT1
Reserved
GPINT0
GPINT1
GPINT2
GPINT3
GPINT4
GPINT5
GPINT6
GPINT7
(1)
(2)
Interrupts 0 through 3 are non-maskable and fixed.
Interrupts 4 through 15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields.
shows the default interrupt sources for Interrupts 4 through 15.
C64x+ Peripheral Information and Electrical Specifications
112
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