www.ti.com
P
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A–APRIL 2006–REVISED DECEMBER 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
MULTICHANNEL BUFFERED SERIAL PORT 1 AND MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP1 and McBSP0)
McBSP external clock source (as opposed to internal) (
I
)
CLKS
AJ4
I
IPD
[shared by McBSP1 and McBSP0]
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKR1/GP[0]
AF4
I/O/Z
IPD
McBSP1 receive clock (
I/O/Z
) or GP[0] (
I/O/Z
) [default]
FSR1/GP[10]
AE5
I/O/Z
IPD
McBSP1 receive frame sync (
I/O/Z
) or GP[10] (
I/O/Z
)[default]
DR1/GP[8]
AH5
I/O/Z
IPD
McBSP1 receive data (
I
) or GP[8] (
I/O/Z
) [default]
DX1/GP[9]
AG5
I/O/Z
IPD
McBSP1 transmit data (
O/Z
) or GP[9] (
I/O/Z
) [default]
FSX1/GP[11]
AG4
I/O/Z
IPD
McBSP1 transmit frame sync (
I/O/Z
) or GP[11] (
I/O/Z
) [default]
CLKX1/GP[3]
AF5
I/O/Z
IPD
McBSP1 transmit clock (
I/O/Z
) or GP[3] (
I/O/Z
) [default]
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKR0
AG1
I/O/Z
IPU
McBSP0 receive clock (
I/O/Z
)
FSR0
AH3
I/O/Z
IPD
McBSP0 receive frame sync (
I/O/Z
)
DR0
AJ5
I
IPD
McBSP0 receive data (
I
)
DX0
AF6
I/O/Z
IPD
McBSP0 transmit data (
O/Z
)
FSX0
AJ3
I/O/Z
IPD
McBSP0 transmit frame sync (
I/O/Z
)
CLKX0
AG6
I/O/Z
IPU
McBSP0 transmit clock (
I/O/Z
)
MANAGEMENT DATA INPUT/OUTPUT (MDIO) FOR MII/RMII/GMII
MDCLK
M5
I/O/Z
IPD
MDIO serial clock (MDCLK) for MII/RMII/RGMII mode (
O
)
MDIO
N3
I/O/Z
IPU
MDIO serial data (MDIO) for MII/RMII/RGMII mode (
I/O
)
MANAGEMENT DATA INPUT/OUTPUT (MDIO) FOR RGMII
RGMDCLK
B4
O/Z
MDIO serial clock for RGMII mode (RGMDCLK) (
O
)
RGMDIO
A4
I/O/Z
MDIO serial data for RGMII mode (RGMDIO) (
I/O
)
ETHERNET MAC (EMAC) [MII/RMII/GMII]
There are two configuration pins — the MAC_SEL[1:0] (AEA[10:9] pins) that select one of the four interface modes (MII, RMII, GMII, or
RGMII) for the EMAC/MDIO interface. For more detailed information on the EMAC configuration pins, see
Section 3
,
Device Configuration
.
This pin is EMAC receive clock (MRCLK) for MII [default] or GMII.
MRCLK
H1
I
MACSEL[1:0] dependent.
This pin is EMAC carrier sense (MCRS) (
I
) for MII [default] or GMII, or EMAC
MCRS/RMCRSDV
J4
I/O/Z
carrier sense/receive data valid (RMCRSDV) (
I
) for RMII. MACSEL[1:0]
dependent.
This pin is EMAC receive error (MRXIR) (
I
) for MII [default], RMII, or GMII.
MRXER/RMRXER
H4
I
MACSEL[1:0] dependent.
This pin is EMAC MII [default] or GMII receive data valid (MRXDV) (
I
).
MRXDV
H5
I
MACSEL[1:0] dependent.
MRXD7
M2
MRXD6
H2
MRXD5
L2
EMAC receive data bus for MII [default], RMII, or GMII
MRXD4
L1
I
These pins function as EMAC receive data pins for MII [default], RMII, or GMII
MRXD3
J3
(MRXD[x:0]) (
I
). MACSEL[1:0] dependent.
MRXD2
J1
MRXD1/RMRXD1
H3
MRXD0/RMRXD0
J2
GMTCLK
K5
O/Z
This pin is EMAC GMII transmit clock (GMTCLK) (
O
). MACSEL[1:0] dependent.
This pin is either EMAC MII [default] or GMII transmit clock (MTCLK) (
I
) or the
EMAC RMII reference clock (RMREFCLK) (
I
). The EMAC function is controlled
MTCLK/RMREFCLK
N4
I
by the MACSEL[1:0] (AEA[10:9] pins). For more detailed information, see
Section 3
,
Device Configuration
.
TYPE
(1)
IPD/IPU
(2)
DESCRIPTION
NO.
Device Overview
34
Submit Documentation Feedback