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7.4.2
EDMA3 Channel Synchronization Events
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A–APRIL 2006–REVISED DECEMBER 2006
The EDMA3 supports up to 64 DMA channels that can be used to service system peripherals and to move
data between system memories. DMA channels can be triggered by synchronization events generated by
system peripherals.
Table 7-3
lists the source of the synchronization event associated with each of the
DMA channels. On the C6454, the association of each synchronization event and DMA channel is fixed
and cannot be reprogrammed.
For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured,
processed, prioritized, linked, chained, and cleared, etc., see the
TMS320C645x DSP Enhanced DMA
(EDMA) Controller User's Guide
(literature number
SPRU966
).
Table 7-3. C6454 EDMA3 Channel Synchronization Events
(1)
EDMA
CHANNEL
0
(2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18-43
44
45
46-47
48
49
50
51
52
53
54
55
56
57
BINARY
EVENT NAME
EVENT DESCRIPTION
000 0000
000 0001
000 0010
000 0011
000 0100
000 0101
000 0110
000 0111
000 1000
000 1001
000 1010
000 1011
000 1100
000 1101
000 1110
000 1111
001 0000
001 0001
-
010 1100
010 1101
-
011 0000
011 0001
011 0010
011 0011
011 0100
011 0101
011 0110
011 0111
011 1000
011 1001
DSP_EVT
TEVTLO0
TEVTHI0
-
-
-
-
-
-
-
-
-
XEVT0
REVT0
XEVT1
REVT1
TEVTLO1
TEVTHI1
-
ICREVT
ICXEVT
-
GPINT0
GPINT1
GPINT2
GPINT3
GPINT4
GPINT5
GPINT6
GPINT7
GPINT8
GPINT9
HPI/PCI-to-DSP event
Timer 0 lower counter event
Timer 0 high counter event
None
None
None
None
None
None
None
None
None
McBSP0 transmit event
McBSP0 receive event
McBSP1 transmit event
McBSP1 receive event
Timer 1 lower counter event
Timer 1 high counter event
None
I2C receive event
I2C transmit event
None
GPIO event 0
GPIO event 1
GPIO event 2
GPIO event 3
GPIO event 4
GPIO event 5
GPIO event 6
GPIO event 7
GPIO event 8
GPIO event 9
(1)
In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate
transfer completion events. For more detailed information on EDMA event-transfer chaining, see the
TMS320C645x DSP Enhanced
DMA (EDMA) Controller User's Guide
(literature number
SPRU966
).
HPI boot and PCI boot are terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event
Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0.
(2)
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