参数资料
型号: TSC2301IZQZR
厂商: TEXAS INSTRUMENTS INC
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA120
封装: GREEN, PLASTIC, VFBGA-120
文件页数: 83/95页
文件大小: 1322K
代理商: TSC2301IZQZR
www.ti.com
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
Table 52. Oscillator Clock Buffer Control
BCKC
Description
0
The output clock buffer is off (default).
1
The output clock buffer is on.
Bit 3 — SMPD
Synchronization Monitor Power Down. This bit turns ON/OFF the I2S bus sync monitor.
Table 53. Synchronization Monitor Power Down
SMPD
Description
0
The I2S bus sync monitor is on (default).
1
The I2S bus sync monitor is off.
Bit 2 — OTSYN
I2S Out Of Sync. This read-only sticky bit reflects the sync status of the I2S bus. It always resets to zero after
being read.
Table 54. I2S Out of Sync
OTSYN
Description
0
The I2S bus is in sync (default).
1
The I2S bus is out of sync.
Bit 1 — BASS
Digital-effects filter control. This bit turns ON/OFF the digital-effects filter. If the digital-effects filter is off, the
signal passes through with no filtering performed.
Table 55. Digital-Effects Filter Control
BASS
Description
0
The digital-effects filter is off (default).
1
The digital-effects filter is on.
Bit 0 — DEEMP
De-emphasis control. This bit turns ON/OFF the de-emphasis function.
Table 56. De-Emphasis Control
DEEMP
Description
0
De-emphasis is off (default).
1
De-emphasis is on.
GPIO CONTROL REGISTER (Page 02, Address 06h)
The GPIO control register controls the GPIO pins of the TSC2301. The direction of each GPIO pin can be set
independently. For GPIOs configured as output pins, the data to be driven is written to this register. For GPIO's
configured as inputs, the input data can be read from this register. This register also contains a bit, SDAVB which
mirrors the state of the DAVB output line.
The GPIO Control Register is formatted as follows:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MSB
LSB
RESV
IO5
IO 4
IO 3
IO 2
IO 1
IO 0
RESV
GPIO5
GPIO4
GPIO3
GPIO2
GPIO
1
0
84
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