参数资料
型号: TSH72CD
厂商: 意法半导体
元件分类: 运动控制电子
英文描述: WIDE BAND, LOW POWER OPERATIONAL AMPLIFIER WITH STANDBY FUNCTION
中文描述: 宽频带低功率运算放大器的待机,功能
文件页数: 20/25页
文件大小: 1096K
代理商: TSH72CD
TSH70, 71, 72, 73, 74, 75
20/25
Video Results:
Precautions on asymmetrical supply
operation:
The TSH7X can be used either with a dual or a
single supply. If a single supply is used, the inputs
are biased to the mid-supply voltage (+Vcc/2).
This bias network must be carefully designed, in
order to reject any noise present on the supply rail.
As the bias current is 15uA, you must carefully
choose the resistance R1 not to introduce an off-
set mismatch at the amplifier inputs.
R1=10K
will be convenient. C1, C2, C3 are by-
pass capacitors from perturbation on Vcc as well
as for the input and output signals. We choose
C1=100nF and C2=C3=100uF.
R2, R3 are such that the current through them
must be superior to 100 times the bias current. So,
we take R2=R3=4.7K
.
Cin, as Cout are chosen to filter the DC signal by
the lowpass filters (R1,Cin) and (Rout, Cout). By
taking R1=10K
, RL=150
,
and Cin=2uF,
Cout=220uF we provide a cutoff frequency below
10Hz.
Use of the TSH7X in gain=-1 configuration:
Some precautions have to be added, specially for
low power supply application.
A feedback capacitance Cf should be added for
better stability. The table summarizes the impact
of the capacitance Cf on the phase margin of the
circuit.
Parameter
Value
Vcc=+-2.5V
0.1
100
100
99.9
99.9
99.9
0
-0.7
0.7
-0.5
-0.7
-0.3
-0.1
-0.4
0
-0.2
0.2
-0.2
-0.1
-0.1
0
-0.2
Value
Vcc=+-5V
0.3
100
99.9
99.8
99.9
99.7
0
-0.6
0.6
-0.3
-0.6
-0.5
-0.3
-0.5
0.1
-0.4
0.5
-0.4
-0.4
-0.3
0.1
-0.1
Unit
Lum NL
Lum NL Step 1
Lum NL Step 2
Lum NL Step 3
Lum NL Step 4
Lum NL Step 5
Diff Gain pos
Diff Gain neg
Diff Gain pp
Diff Gain Step1
Diff Gain Step2
Diff Gain Step3
Diff Gain Step4
Diff Gain Step5
Diff Phase pos
Diff Phase neg
Diff Phase pp
Diff Phase Step1
Diff Phase Step2
Diff Phase Step3
Diff Phase Step4
Diff Phase Step5
%
%
%
%
%
%
%
%
%
%
%
%
%
%
deg
deg
deg
deg
deg
deg
deg
deg
IN
R1
Vcc+
OUT
R2
R3
C1
C3
C2
Cin
Cout
+
-
Cf
R5
R4
RL
IN
R1
Vcc+
OUT
R2
R3
C1
C3
C2
Cin
Cout
+
-
1k
Cf
1k
RL
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