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参数资料
| 型号： | V55C2256164VBT10I |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封装： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件页数： | 7/46页 |
| 文件大小： | 575K |
| 代理商： | V55C2256164VBT10I |
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15
V55C2256164VB Rev. 1.2 May 2007
ProMOS TECHNOLOGIES
V55C2256164VB
Notes for AC Parameters:
1.
For proper power-up see the operation section of this data sheet.
2.
AC timing tests are referenced to the 0.9V crossover point for VCCQ=1.8V components. The transition time is mea-
sured between VIH and VIL. All AC measurements assume tT = 1ns with the AC output load circuit shown in
Figure 1.
4.
If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns has to be added to this parameter.
5.
If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
6.
These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
Refresh Cycle
19
tREF
Refresh Period (8192 cycles)
—
64
—
64
—
64
ms
20
tSREX
Self Refresh Exit Time
1
—
1
—
1
—
CLK
Read Cycle
21
tOH
Data Out Hold Time
3
–
3
–
3
–
ns
2
22
tLZ
Data Out to Low Impedance Time
1
–
1
–
1
–
ns
23
tHZ
Data Out to High Impedance Time
3
7
3
7
3
7
ns
7
24
tDQZ
DQM Data Out Disable Latency
–
2
–
2
–
2
CLK
Write Cycle
25
tWR
Write Recovery Time
1
–
1
–
1
–
CLK
26
tDQW
DQM Write Mask Latency
0
–
0
–
0
–
CLK
#
Symbol Parameter
Limit Values
Unit
Note
-7
-8PC
-10
Min.
Max.
Min.
Max.
Min.
Max.
1.4V
tCS
tCH
tAC
tLZ
tOH
tHZ
CLK
COMMAND
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
VIH
VIL
tT
Figure 1.
tCK
AC Characteristics (Cont’d)
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