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参数资料
| 型号： | V55C3256164VGLK-10IPC |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM, PBGA54 |
| 封装： | GREEN, MO-210, FBGA-54 |
| 文件页数： | 4/55页 |
| 文件大小： | 711K |
| 代理商： | V55C3256164VGLK-10IPC |
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V55C3256164VG Rev. 1.0 September 2008
ProMOS TECHNOLOGIES
V55C3256164VG
Burst Length and Sequence:
Burst
Length
Starting
Address
(A2 A1 A0)
Sequential Burst
Addressing
(decimal)
Interleave Burst
Addressing
(decimal)
2xx0
xx1
0, 1
1, 0
0, 1
1, 0
4x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
8000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
Full Page
nnn
Cn, Cn+1, Cn+2....
not supported
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-
RAS refresh of conventional DRAMs. All of banks must be precharged before applying any refresh mode. An
on-chip address counter increments the word and the bank addresses and no bank information is required
for both refresh modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high
at a clock timing. The mode restores word line after the refresh and no external precharge command is nec-
essary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same
rule applies to any access command after the automatic refresh operation.
The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS, CAS,
and CKE are low and WE is high at a clock timing. All of external control signals including the clock are dis-
abled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit com-
mand, at least one tRC delay is required prior to any access command.
Deep Power Down Mode
The Deep Power Down mode is an unique feature with very low standby currents. All internal voltage gene-
rators inside the Mobile SDRAM are stopped;all memory data is lost in this mode. To enter the Deep Pow-
er Down mode all banks must be precharged.
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