- 您现在的位置：买卖IC网 > PDF目录275205 > V59C1G01164QAUF37H (PROMOS TECHNOLOGIES INC) 64M X 16 DDR DRAM, PBGA92 PDF资料下载
参数资料
| 型号： | V59C1G01164QAUF37H |
| 厂商： | PROMOS TECHNOLOGIES INC |
| 元件分类： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, PBGA92 |
| 封装： | ROHS COMPLIANT, FBGA-92 |
| 文件页数： | 40/79页 |
| 文件大小： | 1028K |
| 代理商： | V59C1G01164QAUF37H |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页当前第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页
45
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QA
V59C1G01(408/808/168)QA Rev. 1.3 June 2008
Burst Write with Auto-Precharge
If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The
DDR2 SDRAM automatically begins precharge operation after the completion of the write burst plus the
write recovery time delay (WR), programmed in the MRS register, as long as tRAS is satisfied. The bank
undergoing Auto-Precharge from the completion of the write burst may be reactivated if the following two con-
ditions are satisfied.
(1) The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied.
(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.
In DDR2 SDRAMs the write recovery time delay (WR ) has to be programmed into the MRS mode register.
As long as the analog tWR timing parameter is not violated, WR can be programmed between 2 and 6 clock
cycles. Minimum Write to Activate command spacing to the same bank = WL + BL/2 + tDAL.
Examples:
Burst Write with Auto-Precharge (tRC Limit) : WL = 2, tDAL = 6 (WR = 3, tRP = 3) , BL = 4
NOP
Bank A
Activate
NOP
WRITE A
T0
T2
T1
T3
T4
T5
T6
T7
NOP
CMD
DQ
BW-AP223
A10 ="high"
tRP
Auto-Precharge Begins
DIN A0 DIN A1 DIN A2 DIN A3
WL = RL-1 = 2
WR
tRCmin.
DQS,
DQS
Completion of the Burst Write
tDAL
>=tRASmin.
CK, CK
相关PDF资料 |
PDF描述 |
|---|---|
| V59C1G01164QALJ19AE | 64M X 16 DDR DRAM, BGA92 |
| V59C1G01164QALF37I | 64M X 16 DDR DRAM, PBGA92 |
| V59C1G01164QALF25H | 64M X 16 DDR DRAM, PBGA92 |
| V62C2801024L-70VI | 128K X 8 STANDARD SRAM, 70 ns, PDSO32 |
| V58C2128804SBT5B | 16M X 8 DDR DRAM, 0.65 ns, PDSO66 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| V5A010CB | 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 PIN PLUNGER |
| V5A010CB | 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 PIN PLUNGER |
| V5A010CB4D | 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER |
| V5A010CB4D | 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER |
| V5A010CB4E | 制造商:Honeywell Sensing and Control 功能描述:MICROSWITCH V5 ROLLER LEVER |
发布紧急采购，3分钟左右您将得到回复。