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参数资料
| 型号： | W3EG2256M72ASSR202AJD3SG |
| 厂商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分类： | DRAM |
| 英文描述： | 512M X 72 DDR DRAM MODULE, 0.8 ns, DMA184 |
| 封装： | ROHS COMPLIANT, DIMM-184 |
| 文件页数： | 10/14页 |
| 文件大小： | 309K |
| 代理商： | W3EG2256M72ASSR202AJD3SG |
W3EG2256M72ASSR-JD3
-AJD3
-BJD3
5
White Electronic Designs
March, 2007
Rev. 4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C TA +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes DDR SDRAM components only
Parameter
Symbol
Rank 1
Conditions
DDR333@
CL=2.5
Max
DDR266@
CL=2, 2.5
Max
DDR200@
CL=2
Max
Units
Rank 2
Standby
State
Operating Current
IDD0
One device bank; Active - Precharge; tRC = tRC
(MIN); tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address and control
inputs changing once every two cycles.
2,340
2,140
mA
IDD2F
Operating Current
IDD1
One device bank; Active-Read-Precharge Burst
= 2; tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA;
Address and control inputs changing once per
clock cycle.
3,060
2,700
2,500
mA
IDD2F
Precharge Power-
Down Standby
Current
IDD2P
All device banks idle; Power-down mode; tCK = tCK
(MIN); CKE = (low)
540
rnA
IDD2P
Idle Standby
Current
IDD2F
CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address and other
control inputs changing once per clock cycle. VIN =
VREF for DQ, DQS and DM.
1,260
1,080
mA
IDD2F
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-Down mode; tCK
(MIN); CKE = (low)
810
mA
IDD2P
Active Standby
Current
IDD3N
CS# = High; CKE = High; One device bank;
Active-Precharge;tRC = tRAS (MAX); tCK = tCK (MIN);
DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing
once per clock cycle.
1,890
1,710
1,610
mA
IDD2F
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); lOUT = 0mA.
3,780
3,420
3,300
mA
IDD3N
Operating Current
IDD4W
Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle.
3,780
3,420
3,300
rnA
IDD3N
Auto Refresh
Current
IDD5
tRC = tRC (MIN)
5,040
4,680
4,500
mA
IDD2F
Self Refresh
Current
IDD6
CKE 0.2V
540
mA
IDD6
Operating Current
IDD7A
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK(MIN);
Address and control inputs change only during
Active Read or Write commands.
7,200
6,660
6,500
mA
IDD3N
Note: These parameters serve to support
SAMSUNG components based modules
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