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参数资料
| 型号： | W942504CH-7 |
| 厂商： | WINBOND ELECTRONICS CORP |
| 元件分类： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封装： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件页数： | 15/45页 |
| 文件大小： | 1261K |
| 代理商： | W942504CH-7 |
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W942504CH
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Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read
command is issued after tRCD from the Bank Activate command, the data is read out sequentially,
synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available
after CAS latency from the issuing of the Read command. The CAS latency must be set in the Mode
Register at power-up.
When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst
operation is terminated.
When the Read with Auto Precharge command is issued, the Precharge operation is performed
automatically after the Read cycle, then the bank is switched to the idle state. This command cannot
be interrupted by any other commands. Refer to the diagrams for Read operation.
Write Operation
Issuing the Write command after tRCD from the bank activate command. The input data is latched
sequentially, synchronizing with both edges(rising &falling) of DQS after the Write command (Burst
write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set
in the Mode Register at power-up.
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst
operation is terminated.
When the Write with Auto Precharge command is issued, the Precharge operation is performed
automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto
Precharge command cannot be interrupted by any other command for the entire burst data duration.
Refer to the diagrams for Write operation.
Precharge
There are two Commands, which perform the precharge operation (Bank Precharge and Precharge
All). When the Bank Precharge command is issued to the active bank, the bank is precharged and
then switched to the idle state. The Bank Precharge command can precharge one bank independently
of the other bank and hold the unprecharged bank in the active state. The maximum time each bank
can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged
within tRAS(max) from the bank activate command.
The Precharge All command can be used to precharge all banks simultaneously. Even if banks are
not in the active state, the Precharge All command can still be issued. In this case, the Precharge
operation is performed only for the active bank and the precharge bank is then switched to the idle
state.
Burst Termination
When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated.
When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after
clock cycle of ( CAS latency) from the Precharge command. When the Burst Write cycle is interrupted
by the Precharge command . the input circuit is reset at the same clock cycle at which the precharge
command is issued. In this case, the DM signal must be asserted "high": during tWR to prevent writing
the invalided data to the cell array.
相关PDF资料 |
PDF描述 |
|---|---|
| W9864G6IH-6 | 4M X 16 DDR DRAM, 5 ns, PDSO54 |
| WA-1RX33-A4 | SNAP ACTING/LIMIT SWITCH |
| WA-A325CBM | Peripheral Interface |
| WA-A325CPC | Peripheral Interface |
| WA-A325CPI | Peripheral Interface |
相关代理商/技术参数 |
参数描述 |
|---|---|
| W942508BH | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DRAM |
| W942508CH | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-5 | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-6 | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
| W942508CH-7 | 制造商:WINBOND 制造商全称:Winbond 功能描述:8M x 4 BANKS x 8 BIT DDR SDRAM |
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