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参数资料
| 型号： | X4045S8ZT1 |
| 厂商： | Intersil |
| 文件页数： | 17/24页 |
| 文件大小： | 0K |
| 描述： | IC CPU SUPERV 4K EEPROM 8-SOIC |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 2,500 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 高有效 |
| 复位超时： | 最小为 100 ms |
| 电压 - 阀值： | 4.38V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
X4043, X4045
CAPACITANCE (T A = 25°C, f = 1.0 MHz, V CC = 5V)
Symbol
Parameter
Max.
Unit
Test Conditions
C OUT
(4)
Output capacitance (SDA, RESET/RESET)
8
pF
V OUT = 0V
C IN(4)
Input capacitance (SCL, WP)
6
pF
V IN = 0V
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
5V
5V
Input pulse levels
Input rise and fall times
0.1 V CC to 0.9 V CC
10ns
1533 ?
For V OL = 0.4V
and I OL = 3 mA
4.6k ?
Input and output timing levels
Output load
0.5 V CC
Standard output load
SDA
100pF
RESET
100pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
100kHz
400kHz
Symbol
f SCL
t IN
t AA
t BUF
t LOW
t HIGH
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO
t DH
Parameter
SCL clock frequency
Pulse width suppression time at inputs
SCL LOW to SDA data out valid
Time the bus free before start of new transmission
Clock LOW time
Clock HIGH time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
Data output hold time
Min.
0
n/a
0.1
4.7
4.7
4.0
4.7
4.0
250
5.0
0.6
50
Max.
100
n/a
0.9
Min.
0
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
Max.
400
0.9
Unit
kHz
ns
μs
μs
μs
μs
μs
μs
ns
μs
μs
ns
t R
SDA and SCL rise time
1000
20 +
.1Cb (6)
300
ns
t F
SDA and SCL fall time
300
20 + .1Cb (6)
300
ns
t SU:WP
t HD:WP
Cb
WP setup time
WP hold time
Capacitive load for each bus line
0.4
0
400
0.6
0
400
μ s
μ s
pF
Notes: (5) Typical values are for T A = 25°C and V CC = 5.0V
(6) Cb = total capacitance of one bus line in pF.
17
FN8118.2
March 16, 2006
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