参数资料
型号: X98021L128-3.3-Z
厂商: INTERSIL CORP
元件分类: 消费家电
英文描述: 210MHz Triple Video Digitizer with Digital PLL
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP128
封装: 14 X 20 MM, ROHS COMPLIANT, MS-022, MQFP-128
文件页数: 24/29页
文件大小: 294K
代理商: X98021L128-3.3-Z
24
FN8219.0
June 2, 2005
.
Initialization
The X98021 initializes with default register settings for an
AC-coupled, RGB input on the VGA1 channel, with a 24 bit
output.
The following registers should be written to fully enable the
chip:
Register 0x1C should be set to 0x49 to improve DPLL
performance in video modes
Register 0x23 should be set to 0x78 to enable the DC
Restore function
Reset
The X98021 has a Power-On Reset (POR) function that
resets the chip to its default state when power is initially
applied, including resetting all the registers to their default
settings as described in the Register Listing. The external
RESET pin duplicates the reset function of the POR without
having to cycle the power supplies. The RESET pin does not
need to be used in normal operation and can be tied high.
Rare CSYNC Considerations
Intersil has discovered one anomaly in its sync separator
function. If the CSYNC signal shown in Figure 11 is present
on the HSYNC input, and the sync source is set to CSYNC
on HSYNC, HS
OUT
may sporadically lock to the wrong edge
of HSYNC
IN
. This will cause the HS
OUT
to have the wrong
position relative to pixel 0, resulting in the image shifting left
or right by the width of the HSYNC
IN
signal for about 1
second before it corrects itself.
This only happens with the exact waveshape shown in
Figure 11. If the polarity of the sync signal is inverted from
that shown in Figure 11, the problem will not occur. If there
are any serrations during the VSYNC period, the problem
will not occur. The problem also will not occur if the sync
signal is on the SOG input.
This is a rarely used composite sync format; in most
applications it will never be encountered. However if this
CSYNC waveform must be supported, there is a simple
applications solution using an XOR gate.
HSYNC
IN
(to A and B)
PIXELCLK (A)
(Internal)
DATA
PRI
(A)
HS
OUT
(A)
DPLL Lock Edge
PIXELCLK = DATACLK Delay
CLKINV
IN
(A) = GND
D
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
P
10
P
11
P
12
P
N-3
P
N-2
P
N-1
P
N
Analog Video In
(to A and B)
DATA
SEC
(A)
DATACLK (A)
D
0
D
2
D
N-3
D
N-1
CLKINV
IN
(B) = GND
D
D
1
D
3
D
N-2
D
N
PIXELCLK (B)
(Internal)
DATA
PRI
(B)
HS
OUT
(B)
DATA
SEC
(B)
DATACLK (B)
FIGURE 10. ALTERNATE PIXEL SAMPLING (48 BIT MODE)
X98021
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