参数资料
型号: XC9536XV-5PC44C
厂商: Xilinx Inc
文件页数: 1/9页
文件大小: 0K
描述: IC CPLD 2.5V ISP 44-PLCC
产品变化通告: XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
标准包装: 26
系列: XC9500XV
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 5.0ns
电压电源 - 内部: 2.37 V ~ 2.62 V
逻辑元件/逻辑块数目: 2
宏单元数: 36
门数: 800
输入/输出数: 34
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.59x16.59)
包装: 管件
DS053 (v3.0) June 25, 2007
1
Product Specification
2006, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Note: This product is being discontinued. You cannot
order parts after May 14, 2008. Xilinx recommends replac-
ing XC9536XV devices with equivalent XC9536XL devices
in all designs as soon as possible. Recommended replace-
ments are pin compatible, however require a VCC change to
3.3V, and a recompile of the design file. In addition, there is
no 1.8V I/O support. See XCN07010 for details regarding
this
discontinuation,
including
device
replacement
recomendations for the XC9536XV CPLD.
Features
36 macrocells with 800 usable gates
Available in small footprint package
-
44-pin VQFP (34 user I/O pins)
Optimized for high-performance 2.5V systems
-
Low power operation
-
Multi-voltage operation
Advanced system features
-
In-system programmable
-
Superior pin-locking and routability with
Fast CONNECT II switch matrix
-
Extra wide 54-input Function Blocks
-
Up to 90 product-terms per macrocell with
individual product-term allocation
-
Local clock inversion with three global and one
product-term clocks
-
Individual output enable per output pin
-
Input hysteresis on all user and boundary-scan pin
inputs
-
Bus-hold circuitry on all user pin inputs
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
20 year data retention
-
ESD protection exceeding 2,000V
Pin-compatible with 3.3V-core XC9536XL device in the
44-pin VQFP package
Description
The XC9536XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of two
54V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for architecture
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
PTOTAL = PINT + PIO = ICCINT x VCCINT + PIO
Separating internal and I/O power here is convenient
because XC9500XV CPLDs also separate the correspond-
ing power pins. PIO is a strong function of the load capaci-
tance driven, so it is handled by I = CVf. ICCINT is another
situation that reflects the actual design considered and the
internal switching speeds. An estimation expression for
ICCINT (taken from simulation) is:
ICCINT(mA) = MCHS(0.122 X PTHS + 0.238) + MCLP(0.042 x
PTLP + 0.171) + 0.04(MCHS + MCLP) x fMAX x MCTOG
where:
MCHS = # macrocells used in high speed mode
MCLP = #macrocells used in low power mode
PTHS = average p-terms used per high speed macrocell
PTLP = average p-terms used over low power macrocell
fMAX = max clocking frequency in the device
MCTOG = % macrocells toggling on each clock (12% is
frequently a good estimate
This calculation was derived from laboratory measurements
of an XC9500XV part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be veri-
fied during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
0
XC9536XV High-performance
CPLD
DS053 (v3.0) June 25, 2007
01
Product Specification
R
Product Obsolete/Under Obsolescence
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