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参数资料
| 型号： | 01AL |
| 英文描述： | 2:1 DIFFERENTIAL-TO-LVPECL MULTIPLEXER |
| 中文描述： | 2:1差分至的LVPECL复用器 |
| 文件页数： | 1/19页 |
| 文件大小： | 301K |
| 代理商： | 01AL |
85301AK
www.icst.com/products/hiperclocks.html
REV. A JANUARY 16, 2006
1
Integrated
Circuit
Systems, Inc.
ICS85301
2:1
DIFFERENTIAL-TO-LVPECL MULTIPLEXER
GENERAL DESCRIPTION
The ICS85301 is a high performance 2:1 Differ-
ential-to-LVPECL Multiplexer and a member of the
HiPerClockSfamily of High Performance Clock
Solutions from ICS. The ICS85301 can also per-
form differential translation because the differ-
ential inputs accept LVPECL, CML as well as LVDS levels.
The ICS85301 is packaged in a small 3mm x 3mm
16 VFQFN package, making it ideal for use on space con-
strained boards.
FEATURES
2:1 LVPECL MUX
One LVPECL output
Two differential clock inputs can accept: LVPECL, LVDS,
CML
Maximum input/output frequency: 3GHz
Translates LVCMOS/LVTTL input signals to LVPECL levels
by using a resistor bias network on nPCLK0, nPCLK0
Propagation delay: 490ps (maximum)
Part-to-part skew: 150ps (maximum)
Additive phase jitter, RMS: 0.009ps (typical)
Full 3.3V or 2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
HiPerClockS
ICS
ICS85301
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
PCLK0
nPCLK0
PCLK1
nPCLK1
VEE
Q
nQ
VEE
V
BB
CLK_SEL
nc
V
CC
nc
V
EE
V
EE
V
CC
1
2
3
4
12
11
10
9
5
6
7
8
16 15 14 13
0
1
PCLK0
nPCLK0
PCLK1
nPCLK1
CLK_SEL
V
BB
Q
nQ
PCLK0
nPCLK0
PCLK1
nPCLK1
VBB
CLK_SEL
nc
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
nc
VEE
VCC
VEE
Q
nQ
VEE
ICS85301
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
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